Module esp32::spi0::cache_sctrl
source · [−]Expand description
Structs
This register you can [read]
(crate::generic::Reg::read), [write_with_zero]
(crate::generic::Reg::write_with_zero), [reset]
(crate::generic::Reg::reset), write
(crate::generic::Reg::write), [modify]
(crate::generic::Reg::modify). See [API]
(https://docs.rs/svd2rust/#read–modify–write-api).
Field CACHE_SRAM_USR_RCMD reader - For SPI0 In the spi sram mode cache read sram for user define command.
Field CACHE_SRAM_USR_RCMD writer - For SPI0 In the spi sram mode cache read sram for user define command.
Field CACHE_SRAM_USR_WCMD reader - For SPI0 In the spi sram mode cache write sram for user define command
Field CACHE_SRAM_USR_WCMD writer - For SPI0 In the spi sram mode cache write sram for user define command
Register CACHE_SCTRL reader
Field SRAM_ADDR_BITLEN reader - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).
Field SRAM_ADDR_BITLEN writer - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).
Field SRAM_BYTES_LEN reader - For SPI0 In the sram mode it is the byte length of spi read sram data.
Field SRAM_BYTES_LEN writer - For SPI0 In the sram mode it is the byte length of spi read sram data.
Field SRAM_DUMMY_CYCLELEN reader - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).
Field SRAM_DUMMY_CYCLELEN writer - For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).
Field USR_RD_SRAM_DUMMY reader - For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.
Field USR_RD_SRAM_DUMMY writer - For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.
Field USR_SRAM_DIO reader - For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable
Field USR_SRAM_DIO writer - For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable
Field USR_SRAM_QIO reader - For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable
Field USR_SRAM_QIO writer - For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable
Field USR_WR_SRAM_DUMMY reader - For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.
Field USR_WR_SRAM_DUMMY writer - For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.
Register CACHE_SCTRL writer