Module esp32::rmt::int_st

Expand description

Structs

Field CH0_ERR_INT_ST reader - The interrupt state bit for channel 0’s rmt_ch0_err_int_raw when rmt_ch0_err_int_ena is set to 0.

CH0_RX_END_INT_ST_R

Field CH0_RX_END_INT_ST reader - The interrupt state bit for channel 0’s rmt_ch0_rx_end_int_raw when rmt_ch0_rx_end_int_ena is set to 0.

CH0_TX_END_INT_ST_R

Field CH0_TX_END_INT_ST reader - The interrupt state bit for channel 0’s mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.

CH0_TX_THR_EVENT_INT_ST_R

Field CH0_TX_THR_EVENT_INT_ST reader - The interrupt state bit for channel 0’s rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.

CH1_ERR_INT_ST_R

Field CH1_ERR_INT_ST reader - The interrupt state bit for channel 1’s rmt_ch1_err_int_raw when rmt_ch1_err_int_ena is set to 1.

CH1_RX_END_INT_ST_R

Field CH1_RX_END_INT_ST reader - The interrupt state bit for channel 1’s rmt_ch1_rx_end_int_raw when rmt_ch1_rx_end_int_ena is set to 1.

CH1_TX_END_INT_ST_R

Field CH1_TX_END_INT_ST reader - The interrupt state bit for channel 1’s mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.

CH1_TX_THR_EVENT_INT_ST_R

Field CH1_TX_THR_EVENT_INT_ST reader - The interrupt state bit for channel 1’s rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.

CH2_ERR_INT_ST_R

Field CH2_ERR_INT_ST reader - The interrupt state bit for channel 2’s rmt_ch2_err_int_raw when rmt_ch2_err_int_ena is set to 1.

CH2_RX_END_INT_ST_R

Field CH2_RX_END_INT_ST reader - The interrupt state bit for channel 2’s rmt_ch2_rx_end_int_raw when rmt_ch2_rx_end_int_ena is set to 1.

CH2_TX_END_INT_ST_R

Field CH2_TX_END_INT_ST reader - The interrupt state bit for channel 2’s mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.

CH2_TX_THR_EVENT_INT_ST_R

Field CH2_TX_THR_EVENT_INT_ST reader - The interrupt state bit for channel 2’s rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.

CH3_ERR_INT_ST_R

Field CH3_ERR_INT_ST reader - The interrupt state bit for channel 3’s rmt_ch3_err_int_raw when rmt_ch3_err_int_ena is set to 1.

CH3_RX_END_INT_ST_R

Field CH3_RX_END_INT_ST reader - The interrupt state bit for channel 3’s rmt_ch3_rx_end_int_raw when rmt_ch3_rx_end_int_ena is set to 1.

CH3_TX_END_INT_ST_R

Field CH3_TX_END_INT_ST reader - The interrupt state bit for channel 3’s mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.

CH3_TX_THR_EVENT_INT_ST_R

Field CH3_TX_THR_EVENT_INT_ST reader - The interrupt state bit for channel 3’s rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.

CH4_ERR_INT_ST_R

Field CH4_ERR_INT_ST reader - The interrupt state bit for channel 4’s rmt_ch4_err_int_raw when rmt_ch4_err_int_ena is set to 1.

CH4_RX_END_INT_ST_R

Field CH4_RX_END_INT_ST reader - The interrupt state bit for channel 4’s rmt_ch4_rx_end_int_raw when rmt_ch4_rx_end_int_ena is set to 1.

CH4_TX_END_INT_ST_R

Field CH4_TX_END_INT_ST reader - The interrupt state bit for channel 4’s mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.

CH4_TX_THR_EVENT_INT_ST_R

Field CH4_TX_THR_EVENT_INT_ST reader - The interrupt state bit for channel 4’s rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.

CH5_ERR_INT_ST_R

Field CH5_ERR_INT_ST reader - The interrupt state bit for channel 5’s rmt_ch5_err_int_raw when rmt_ch5_err_int_ena is set to 1.

CH5_RX_END_INT_ST_R

Field CH5_RX_END_INT_ST reader - The interrupt state bit for channel 5’s rmt_ch5_rx_end_int_raw when rmt_ch5_rx_end_int_ena is set to 1.

CH5_TX_END_INT_ST_R

Field CH5_TX_END_INT_ST reader - The interrupt state bit for channel 5’s mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.

CH5_TX_THR_EVENT_INT_ST_R

Field CH5_TX_THR_EVENT_INT_ST reader - The interrupt state bit for channel 5’s rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.

CH6_ERR_INT_ST_R

Field CH6_ERR_INT_ST reader - The interrupt state bit for channel 6’s rmt_ch6_err_int_raw when rmt_ch6_err_int_ena is set to 1.

CH6_RX_END_INT_ST_R

Field CH6_RX_END_INT_ST reader - The interrupt state bit for channel 6’s rmt_ch6_rx_end_int_raw when rmt_ch6_rx_end_int_ena is set to 1.

CH6_TX_END_INT_ST_R

Field CH6_TX_END_INT_ST reader - The interrupt state bit for channel 6’s mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.

CH6_TX_THR_EVENT_INT_ST_R

Field CH6_TX_THR_EVENT_INT_ST reader - The interrupt state bit for channel 6’s rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.

CH7_ERR_INT_ST_R

Field CH7_ERR_INT_ST reader - The interrupt state bit for channel 7’s rmt_ch7_err_int_raw when rmt_ch7_err_int_ena is set to 1.

CH7_RX_END_INT_ST_R

Field CH7_RX_END_INT_ST reader - The interrupt state bit for channel 7’s rmt_ch7_rx_end_int_raw when rmt_ch7_rx_end_int_ena is set to 1.

CH7_TX_END_INT_ST_R

Field CH7_TX_END_INT_ST reader - The interrupt state bit for channel 7’s mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.

CH7_TX_THR_EVENT_INT_ST_R

Field CH7_TX_THR_EVENT_INT_ST reader - The interrupt state bit for channel 7’s rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.

INT_ST_SPEC

This register you can [read] (crate::generic::Reg::read). See [API] (https://docs.rs/svd2rust/#read–modify–write-api).

R

Register INT_ST reader