[][src]Type Definition esp32::uart::uart_int_raw_reg::R

type R = R<u32, UART_INT_RAW_REG>;

Reader of register UART_INT_RAW_REG

Methods

impl R[src]

pub fn uart_at_cmd_char_det_int_raw(&self) -> UART_AT_CMD_CHAR_DET_INT_RAW_R[src]

Bit 18 - This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.

pub fn uart_rs485_clash_int_raw(&self) -> UART_RS485_CLASH_INT_RAW_R[src]

Bit 17 - This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.

pub fn uart_rs485_frm_err_int_raw(&self) -> UART_RS485_FRM_ERR_INT_RAW_R[src]

Bit 16 - This interrupt raw bit turns to high level when rs485 detects the data frame error.

pub fn uart_rs485_parity_err_int_raw(&self) -> UART_RS485_PARITY_ERR_INT_RAW_R[src]

Bit 15 - This interrupt raw bit turns to high level when rs485 detects the parity error.

pub fn uart_tx_done_int_raw(&self) -> UART_TX_DONE_INT_RAW_R[src]

Bit 14 - This interrupt raw bit turns to high level when transmitter has send all the data in fifo.

pub fn uart_tx_brk_idle_done_int_raw(&self) -> UART_TX_BRK_IDLE_DONE_INT_RAW_R[src]

Bit 13 - This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the last data has been send.

pub fn uart_tx_brk_done_int_raw(&self) -> UART_TX_BRK_DONE_INT_RAW_R[src]

Bit 12 - This interrupt raw bit turns to high level when transmitter completes sendding 0 after all the datas in transmitter's fifo are send.

pub fn uart_glitch_det_int_raw(&self) -> UART_GLITCH_DET_INT_RAW_R[src]

Bit 11 - This interrupt raw bit turns to high level when receiver detects the start bit.

pub fn uart_sw_xoff_int_raw(&self) -> UART_SW_XOFF_INT_RAW_R[src]

Bit 10 - This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.

pub fn uart_sw_xon_int_raw(&self) -> UART_SW_XON_INT_RAW_R[src]

Bit 9 - This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.

pub fn uart_rxfifo_tout_int_raw(&self) -> UART_RXFIFO_TOUT_INT_RAW_R[src]

Bit 8 - This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.

pub fn uart_brk_det_int_raw(&self) -> UART_BRK_DET_INT_RAW_R[src]

Bit 7 - This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.

pub fn uart_cts_chg_int_raw(&self) -> UART_CTS_CHG_INT_RAW_R[src]

Bit 6 - This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.

pub fn uart_dsr_chg_int_raw(&self) -> UART_DSR_CHG_INT_RAW_R[src]

Bit 5 - This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.

pub fn uart_rxfifo_ovf_int_raw(&self) -> UART_RXFIFO_OVF_INT_RAW_R[src]

Bit 4 - This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.

pub fn uart_frm_err_int_raw(&self) -> UART_FRM_ERR_INT_RAW_R[src]

Bit 3 - This interrupt raw bit turns to high level when receiver detects data's frame error .

pub fn uart_parity_err_int_raw(&self) -> UART_PARITY_ERR_INT_RAW_R[src]

Bit 2 - This interrupt raw bit turns to high level when receiver detects the parity error of data.

pub fn uart_txfifo_empty_int_raw(&self) -> UART_TXFIFO_EMPTY_INT_RAW_R[src]

Bit 1 - This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .

pub fn uart_rxfifo_full_int_raw(&self) -> UART_RXFIFO_FULL_INT_RAW_R[src]

Bit 0 - This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).