Type Definition esp32::timg::timg_wdtconfig0_reg::W

type W = W<u32, TIMG_WDTCONFIG0_REG>;

Writer for register TIMG_WDTCONFIG0_REG

Methods

impl W

pub fn timg_wdt_en(&mut self) -> TIMG_WDT_EN_W

Bit 31 - When set SWDT is enabled

pub fn timg_wdt_stg0(&mut self) -> TIMG_WDT_STG0_W

Bits 29:30 - Stage 0 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system

pub fn timg_wdt_stg1(&mut self) -> TIMG_WDT_STG1_W

Bits 27:28 - Stage 1 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system

pub fn timg_wdt_stg2(&mut self) -> TIMG_WDT_STG2_W

Bits 25:26 - Stage 2 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system

pub fn timg_wdt_stg3(&mut self) -> TIMG_WDT_STG3_W

Bits 23:24 - Stage 3 configuration. 0: off 1: interrupt 2: reset CPU 3: reset system

pub fn timg_wdt_edge_int_en(&mut self) -> TIMG_WDT_EDGE_INT_EN_W

Bit 22 - When set edge type interrupt generation is enabled

pub fn timg_wdt_level_int_en(&mut self) -> TIMG_WDT_LEVEL_INT_EN_W

Bit 21 - When set level type interrupt generation is enabled

pub fn timg_wdt_cpu_reset_length(&mut self) -> TIMG_WDT_CPU_RESET_LENGTH_W

Bits 18:20 - length of CPU reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us

pub fn timg_wdt_sys_reset_length(&mut self) -> TIMG_WDT_SYS_RESET_LENGTH_W

Bits 15:17 - length of system reset selection. 0: 100ns 1: 200ns 2: 300ns 3: 400ns 4: 500ns 5: 800ns 6: 1.6us 7: 3.2us

pub fn timg_wdt_flashboot_mod_en(&mut self) -> TIMG_WDT_FLASHBOOT_MOD_EN_W

Bit 14 - When set flash boot protection is enabled