[−][src]Type Definition esp32::spi::spi_pin_reg::W
type W = W<u32, SPI_PIN_REG>;
Writer for register SPI_PIN_REG
Methods
impl W
[src]
pub fn spi_cs_keep_active(&mut self) -> SPI_CS_KEEP_ACTIVE_W
[src]
Bit 30 - spi cs line keep low when the bit is set.
pub fn spi_ck_idle_edge(&mut self) -> SPI_CK_IDLE_EDGE_W
[src]
Bit 29 - 1: spi clk line is high when idle 0: spi clk line is low when idle
pub fn spi_master_ck_sel(&mut self) -> SPI_MASTER_CK_SEL_W
[src]
Bits 11:13 - In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.
pub fn spi_master_cs_pol(&mut self) -> SPI_MASTER_CS_POL_W
[src]
Bits 6:8 - In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.
pub fn spi_ck_dis(&mut self) -> SPI_CK_DIS_W
[src]
Bit 5 - 1: spi clk out disable 0: spi clk out enable
pub fn spi_cs2_dis(&mut self) -> SPI_CS2_DIS_W
[src]
Bit 2 - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin
pub fn spi_cs1_dis(&mut self) -> SPI_CS1_DIS_W
[src]
Bit 1 - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin
pub fn spi_cs0_dis(&mut self) -> SPI_CS0_DIS_W
[src]
Bit 0 - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin