Type Definition esp32::rtccntl::rtc_cntl_clk_conf_reg::R

type R = R<u32, RTC_CNTL_CLK_CONF_REG>;

Reader of register RTC_CNTL_CLK_CONF_REG

Methods

impl R

pub fn rtc_cntl_ana_clk_rtc_sel(&self) -> RTC_CNTL_ANA_CLK_RTC_SEL_R

Bits 30:31 - slow_clk_rtc sel. 0: SLOW_CK 1: CK_XTAL_32K 2: CK8M_D256_OUT

pub fn rtc_cntl_fast_clk_rtc_sel(&self) -> RTC_CNTL_FAST_CLK_RTC_SEL_R

Bit 29 - fast_clk_rtc sel. 0: XTAL div 4 1: CK8M

pub fn rtc_cntl_soc_clk_sel(&self) -> RTC_CNTL_SOC_CLK_SEL_R

Bits 27:28 - SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL

pub fn rtc_cntl_ck8m_force_pu(&self) -> RTC_CNTL_CK8M_FORCE_PU_R

Bit 26 - CK8M force power up

pub fn rtc_cntl_ck8m_force_pd(&self) -> RTC_CNTL_CK8M_FORCE_PD_R

Bit 25 - CK8M force power down

pub fn rtc_cntl_ck8m_dfreq(&self) -> RTC_CNTL_CK8M_DFREQ_R

Bits 17:24 - CK8M_DFREQ

pub fn rtc_cntl_ck8m_force_nogating(&self) -> RTC_CNTL_CK8M_FORCE_NOGATING_R

Bit 16 - CK8M force no gating during sleep

pub fn rtc_cntl_xtal_force_nogating(&self) -> RTC_CNTL_XTAL_FORCE_NOGATING_R

Bit 15 - XTAL force no gating during sleep

pub fn rtc_cntl_ck8m_div_sel(&self) -> RTC_CNTL_CK8M_DIV_SEL_R

Bits 12:14 - divider = reg_ck8m_div_sel + 1

pub fn rtc_cntl_ck8m_dfreq_force(&self) -> RTC_CNTL_CK8M_DFREQ_FORCE_R

Bit 11

pub fn rtc_cntl_dig_clk8m_en(&self) -> RTC_CNTL_DIG_CLK8M_EN_R

Bit 10 - enable CK8M for digital core (no relationship with RTC core)

pub fn rtc_cntl_dig_clk8m_d256_en(&self) -> RTC_CNTL_DIG_CLK8M_D256_EN_R

Bit 9 - enable CK8M_D256_OUT for digital core (no relationship with RTC core)

pub fn rtc_cntl_dig_xtal32k_en(&self) -> RTC_CNTL_DIG_XTAL32K_EN_R

Bit 8 - enable CK_XTAL_32K for digital core (no relationship with RTC core)

pub fn rtc_cntl_enb_ck8m_div(&self) -> RTC_CNTL_ENB_CK8M_DIV_R

Bit 7 - 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by 256

pub fn rtc_cntl_enb_ck8m(&self) -> RTC_CNTL_ENB_CK8M_R

Bit 6 - disable CK8M and CK8M_D256_OUT

pub fn rtc_cntl_ck8m_div(&self) -> RTC_CNTL_CK8M_DIV_R

Bits 4:5 - CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: div1024.