Type Definition esp32::rmt::rmt_ch0conf1_reg::W

type W = W<u32, RMT_CH0CONF1_REG>;

Writer for register RMT_CH0CONF1_REG

Methods

impl W

pub fn rmt_idle_out_en_ch0(&mut self) -> RMT_IDLE_OUT_EN_CH0_W

Bit 19 - This is the output enable control bit for channel0 in IDLE state.

pub fn rmt_idle_out_lv_ch0(&mut self) -> RMT_IDLE_OUT_LV_CH0_W

Bit 18 - This bit configures the output signal's level for channel0 in IDLE state.

pub fn rmt_ref_always_on_ch0(&mut self) -> RMT_REF_ALWAYS_ON_CH0_W

Bit 17 - This bit is used to select base clock. 1'b1:clk_apb 1'b0:clk_ref

pub fn rmt_ref_cnt_rst_ch0(&mut self) -> RMT_REF_CNT_RST_CH0_W

Bit 16 - This bit is used to reset divider in channel0.

pub fn rmt_rx_filter_thres_ch0(&mut self) -> RMT_RX_FILTER_THRES_CH0_W

Bits 8:15 - in receive mode channel0 ignore input pulse when the pulse width is smaller then this value.

pub fn rmt_rx_filter_en_ch0(&mut self) -> RMT_RX_FILTER_EN_CH0_W

Bit 7 - This is the receive filter enable bit for channel0.

pub fn rmt_tx_conti_mode_ch0(&mut self) -> RMT_TX_CONTI_MODE_CH0_W

Bit 6 - Set this bit to continue sending from the first data to the last data in channel0 again and again.

pub fn rmt_mem_owner_ch0(&mut self) -> RMT_MEM_OWNER_CH0_W

Bit 5 - This is the mark of channel0's ram usage right.1'b1：receiver uses the ram 0：transmitter uses the ram

pub fn rmt_apb_mem_rst_ch0(&mut self) -> RMT_APB_MEM_RST_CH0_W

Bit 4 - Set this bit to reset W/R ram address for channel0 by apb fifo access

pub fn rmt_mem_rd_rst_ch0(&mut self) -> RMT_MEM_RD_RST_CH0_W

Bit 3 - Set this bit to reset read ram address for channel0 by transmitter access.

pub fn rmt_mem_wr_rst_ch0(&mut self) -> RMT_MEM_WR_RST_CH0_W

Bit 2 - Set this bit to reset write ram address for channel0 by receiver access.

pub fn rmt_rx_en_ch0(&mut self) -> RMT_RX_EN_CH0_W

Bit 1 - Set this bit to enbale receving data for channel0.

pub fn rmt_tx_start_ch0(&mut self) -> RMT_TX_START_CH0_W

Bit 0 - Set this bit to start sending data for channel0.