Type Definition esp32::mcpwm::mcmcpwm_int_st_mcpwm_reg::R

type R = R<u32, MCMCPWM_INT_ST_MCPWM_REG>;

Reader of register MCMCPWM_INT_ST_MCPWM_REG

Methods

impl R

pub fn mcpwm_cap2_int_st(&self) -> MCPWM_CAP2_INT_ST_R

Bit 29 - The masked status bit for interrupt triggered by captureon channel 2

pub fn mcpwm_cap1_int_st(&self) -> MCPWM_CAP1_INT_ST_R

Bit 28 - The masked status bit for interrupt triggered by captureon channel 1

pub fn mcpwm_cap0_int_st(&self) -> MCPWM_CAP0_INT_ST_R

Bit 27 - The masked status bit for interrupt triggered by captureon channel 0

pub fn mcpwm_fh2_ost_int_st(&self) -> MCPWM_FH2_OST_INT_ST_R

Bit 26 - The masked status bit for interrupt triggered by an one-shot mode action on PWM2

pub fn mcpwm_fh1_ost_int_st(&self) -> MCPWM_FH1_OST_INT_ST_R

Bit 25 - The masked status bit for interrupt triggered by an one-shot mode action on PWM0

pub fn mcpwm_fh0_ost_int_st(&self) -> MCPWM_FH0_OST_INT_ST_R

Bit 24 - The masked status bit for interrupt triggered by an one-shot mode action on PWM0

pub fn mcpwm_fh2_cbc_int_st(&self) -> MCPWM_FH2_CBC_INT_ST_R

Bit 23 - The masked status bit for interrupt triggered by an cycle-by-cycle mode action on PWM2

pub fn mcpwm_fh1_cbc_int_st(&self) -> MCPWM_FH1_CBC_INT_ST_R

Bit 22 - The masked status bit for interrupt triggered by an cycle-by-cycle mode action on PWM1

pub fn mcpwm_fh0_cbc_int_st(&self) -> MCPWM_FH0_CBC_INT_ST_R

Bit 21 - The masked status bit for interrupt triggered by an cycle-by-cycle mode action on PWM0

pub fn mcpwm_op2_teb_int_st(&self) -> MCPWM_OP2_TEB_INT_ST_R

Bit 20 - The masked status bit for interrupt triggered by a PWM operator 2 TEB event

pub fn mcpwm_op1_teb_int_st(&self) -> MCPWM_OP1_TEB_INT_ST_R

Bit 19 - The masked status bit for interrupt triggered by a PWM operator 1 TEB event

pub fn mcpwm_op0_teb_int_st(&self) -> MCPWM_OP0_TEB_INT_ST_R

Bit 18 - The masked status bit for interrupt triggered by a PWM operator 0 TEB event

pub fn mcpwm_op2_tea_int_st(&self) -> MCPWM_OP2_TEA_INT_ST_R

Bit 17 - The masked status bit for interrupt triggered by a PWM operator 2 TEA event

pub fn mcpwm_op1_tea_int_st(&self) -> MCPWM_OP1_TEA_INT_ST_R

Bit 16 - The masked status bit for interrupt triggered by a PWM operator 1 TEA event

pub fn mcpwm_op0_tea_int_st(&self) -> MCPWM_OP0_TEA_INT_ST_R

Bit 15 - The masked status bit for interrupt triggered by a PWM operator 0 TEA event

pub fn mcpwm_fault2_clr_int_st(&self) -> MCPWM_FAULT2_CLR_INT_ST_R

Bit 14 - The masked status bit for interrupt triggered when event_f2 ends

pub fn mcpwm_fault1_clr_int_st(&self) -> MCPWM_FAULT1_CLR_INT_ST_R

Bit 13 - The masked status bit for interrupt triggered when event_f1 ends

pub fn mcpwm_fault0_clr_int_st(&self) -> MCPWM_FAULT0_CLR_INT_ST_R

Bit 12 - The masked status bit for interrupt triggered when event_f0 ends

pub fn mcpwm_fault2_int_st(&self) -> MCPWM_FAULT2_INT_ST_R

Bit 11 - The masked status bit for interrupt triggered when event_f2 starts

pub fn mcpwm_fault1_int_st(&self) -> MCPWM_FAULT1_INT_ST_R

Bit 10 - The masked status bit for interrupt triggered when event_f1 starts

pub fn mcpwm_fault0_int_st(&self) -> MCPWM_FAULT0_INT_ST_R

Bit 9 - The masked status bit for interrupt triggered when event_f0 starts

pub fn mcpwm_timer2_tep_int_st(&self) -> MCPWM_TIMER2_TEP_INT_ST_R

Bit 8 - The masked status bit for interrupt triggered by a PWM timer 2 TEP event

pub fn mcpwm_timer1_tep_int_st(&self) -> MCPWM_TIMER1_TEP_INT_ST_R

Bit 7 - The masked status bit for interrupt triggered by a PWM timer 1 TEP event

pub fn mcpwm_timer0_tep_int_st(&self) -> MCPWM_TIMER0_TEP_INT_ST_R

Bit 6 - The masked status bit for interrupt triggered by a PWM timer 0 TEP event

pub fn mcpwm_timer2_tez_int_st(&self) -> MCPWM_TIMER2_TEZ_INT_ST_R

Bit 5 - The masked status bit for interrupt triggered by a PWM timer 2 TEZ event

pub fn mcpwm_timer1_tez_int_st(&self) -> MCPWM_TIMER1_TEZ_INT_ST_R

Bit 4 - The masked status bit for interrupt triggered by a PWM timer 1 TEZ event

pub fn mcpwm_timer0_tez_int_st(&self) -> MCPWM_TIMER0_TEZ_INT_ST_R

Bit 3 - The masked status bit for interrupt triggered by a PWM timer 0 TEZ event

pub fn mcpwm_timer2_stop_int_st(&self) -> MCPWM_TIMER2_STOP_INT_ST_R

Bit 2 - The masked status bit for interrupt triggered when timer 2 stops

pub fn mcpwm_timer1_stop_int_st(&self) -> MCPWM_TIMER1_STOP_INT_ST_R

Bit 1 - The masked status bit for interrupt triggered when timer 1 stops

pub fn mcpwm_timer0_stop_int_st(&self) -> MCPWM_TIMER0_STOP_INT_ST_R

Bit 0 - The masked status bit for interrupt triggered when timer 0 stops