[−][src]Type Definition esp32::mcpwm::mcmcpwm_int_raw_mcpwm_reg::R
type R = R<u32, MCMCPWM_INT_RAW_MCPWM_REG>;
Reader of register MCMCPWM_INT_RAW_MCPWM_REG
Methods
impl R
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pub fn mcpwm_cap2_int_raw(&self) -> MCPWM_CAP2_INT_RAW_R
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Bit 29 - The raw status bit for interrupt triggered by captureon channel 2
pub fn mcpwm_cap1_int_raw(&self) -> MCPWM_CAP1_INT_RAW_R
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Bit 28 - The raw status bit for interrupt triggered by captureon channel 1
pub fn mcpwm_cap0_int_raw(&self) -> MCPWM_CAP0_INT_RAW_R
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Bit 27 - The raw status bit for interrupt triggered by captureon channel 0
pub fn mcpwm_fh2_ost_int_raw(&self) -> MCPWM_FH2_OST_INT_RAW_R
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Bit 26 - The raw status bit for interrupt triggered by an one-shot mode action on PWM2
pub fn mcpwm_fh1_ost_int_raw(&self) -> MCPWM_FH1_OST_INT_RAW_R
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Bit 25 - The raw status bit for interrupt triggered by an one-shot mode action on PWM0
pub fn mcpwm_fh0_ost_int_raw(&self) -> MCPWM_FH0_OST_INT_RAW_R
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Bit 24 - The raw status bit for interrupt triggered by an one-shot mode action on PWM0
pub fn mcpwm_fh2_cbc_int_raw(&self) -> MCPWM_FH2_CBC_INT_RAW_R
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Bit 23 - The raw status bit for interrupt triggered by an cycle-by-cycle mode action on PWM2
pub fn mcpwm_fh1_cbc_int_raw(&self) -> MCPWM_FH1_CBC_INT_RAW_R
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Bit 22 - The raw status bit for interrupt triggered by an cycle-by-cycle mode action on PWM1
pub fn mcpwm_fh0_cbc_int_raw(&self) -> MCPWM_FH0_CBC_INT_RAW_R
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Bit 21 - The raw status bit for interrupt triggered by an cycle-by-cycle mode action on PWM0
pub fn mcpwm_op2_teb_int_raw(&self) -> MCPWM_OP2_TEB_INT_RAW_R
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Bit 20 - The raw status bit for interrupt triggered by a PWM operator 2 TEB event
pub fn mcpwm_op1_teb_int_raw(&self) -> MCPWM_OP1_TEB_INT_RAW_R
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Bit 19 - The raw status bit for interrupt triggered by a PWM operator 1 TEB event
pub fn mcpwm_op0_teb_int_raw(&self) -> MCPWM_OP0_TEB_INT_RAW_R
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Bit 18 - The raw status bit for interrupt triggered by a PWM operator 0 TEB event
pub fn mcpwm_op2_tea_int_raw(&self) -> MCPWM_OP2_TEA_INT_RAW_R
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Bit 17 - The raw status bit for interrupt triggered by a PWM operator 2 TEA event
pub fn mcpwm_op1_tea_int_raw(&self) -> MCPWM_OP1_TEA_INT_RAW_R
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Bit 16 - The raw status bit for interrupt triggered by a PWM operator 1 TEA event
pub fn mcpwm_op0_tea_int_raw(&self) -> MCPWM_OP0_TEA_INT_RAW_R
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Bit 15 - The raw status bit for interrupt triggered by a PWM operator 0 TEA event
pub fn mcpwm_fault2_clr_int_raw(&self) -> MCPWM_FAULT2_CLR_INT_RAW_R
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Bit 14 - The raw status bit for interrupt triggered when event_f2 ends
pub fn mcpwm_fault1_clr_int_raw(&self) -> MCPWM_FAULT1_CLR_INT_RAW_R
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Bit 13 - The raw status bit for interrupt triggered when event_f1 ends
pub fn mcpwm_fault0_clr_int_raw(&self) -> MCPWM_FAULT0_CLR_INT_RAW_R
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Bit 12 - The raw status bit for interrupt triggered when event_f0 ends
pub fn mcpwm_fault2_int_raw(&self) -> MCPWM_FAULT2_INT_RAW_R
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Bit 11 - The raw status bit for interrupt triggered when event_f2 starts
pub fn mcpwm_fault1_int_raw(&self) -> MCPWM_FAULT1_INT_RAW_R
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Bit 10 - The raw status bit for interrupt triggered when event_f1 starts
pub fn mcpwm_fault0_int_raw(&self) -> MCPWM_FAULT0_INT_RAW_R
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Bit 9 - The raw status bit for interrupt triggered when event_f0 starts
pub fn mcpwm_timer2_tep_int_raw(&self) -> MCPWM_TIMER2_TEP_INT_RAW_R
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Bit 8 - The raw status bit for interrupt triggered by a PWM timer 2 TEP event
pub fn mcpwm_timer1_tep_int_raw(&self) -> MCPWM_TIMER1_TEP_INT_RAW_R
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Bit 7 - The raw status bit for interrupt triggered by a PWM timer 1 TEP event
pub fn mcpwm_timer0_tep_int_raw(&self) -> MCPWM_TIMER0_TEP_INT_RAW_R
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Bit 6 - The raw status bit for interrupt triggered by a PWM timer 0 TEP event
pub fn mcpwm_timer2_tez_int_raw(&self) -> MCPWM_TIMER2_TEZ_INT_RAW_R
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Bit 5 - The raw status bit for interrupt triggered by a PWM timer 2 TEZ event
pub fn mcpwm_timer1_tez_int_raw(&self) -> MCPWM_TIMER1_TEZ_INT_RAW_R
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Bit 4 - The raw status bit for interrupt triggered by a PWM timer 1 TEZ event
pub fn mcpwm_timer0_tez_int_raw(&self) -> MCPWM_TIMER0_TEZ_INT_RAW_R
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Bit 3 - The raw status bit for interrupt triggered by a PWM timer 0 TEZ event
pub fn mcpwm_timer2_stop_int_raw(&self) -> MCPWM_TIMER2_STOP_INT_RAW_R
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Bit 2 - The raw status bit for interrupt triggered when timer 2 stops
pub fn mcpwm_timer1_stop_int_raw(&self) -> MCPWM_TIMER1_STOP_INT_RAW_R
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Bit 1 - The raw status bit for interrupt triggered when timer 1 stops
pub fn mcpwm_timer0_stop_int_raw(&self) -> MCPWM_TIMER0_STOP_INT_RAW_R
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Bit 0 - The raw status bit for interrupt triggered when timer 0 stops