[][src]Struct esp32::i2s::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub i2s_conf_reg: I2S_CONF_REG,
    pub i2s_int_raw_reg: I2S_INT_RAW_REG,
    pub i2s_int_st_reg: I2S_INT_ST_REG,
    pub i2s_int_ena_reg: I2S_INT_ENA_REG,
    pub i2s_int_clr_reg: I2S_INT_CLR_REG,
    pub i2s_timing_reg: I2S_TIMING_REG,
    pub i2s_fifo_conf_reg: I2S_FIFO_CONF_REG,
    pub i2s_rxeof_num_reg: I2S_RXEOF_NUM_REG,
    pub i2s_conf_sigle_data_reg: I2S_CONF_SIGLE_DATA_REG,
    pub i2s_conf_chan_reg: I2S_CONF_CHAN_REG,
    pub i2s_out_link_reg: I2S_OUT_LINK_REG,
    pub i2s_in_link_reg: I2S_IN_LINK_REG,
    pub i2s_out_eof_des_addr_reg: I2S_OUT_EOF_DES_ADDR_REG,
    pub i2s_in_eof_des_addr_reg: I2S_IN_EOF_DES_ADDR_REG,
    pub i2s_out_eof_bfr_des_addr_reg: I2S_OUT_EOF_BFR_DES_ADDR_REG,
    pub i2s_ahb_test_reg: I2S_AHB_TEST_REG,
    pub i2s_inlink_dscr_reg: I2S_INLINK_DSCR_REG,
    pub i2s_inlink_dscr_bf0_reg: I2S_INLINK_DSCR_BF0_REG,
    pub i2s_inlink_dscr_bf1_reg: I2S_INLINK_DSCR_BF1_REG,
    pub i2s_outlink_dscr_reg: I2S_OUTLINK_DSCR_REG,
    pub i2s_outlink_dscr_bf0_reg: I2S_OUTLINK_DSCR_BF0_REG,
    pub i2s_outlink_dscr_bf1_reg: I2S_OUTLINK_DSCR_BF1_REG,
    pub i2s_lc_conf_reg: I2S_LC_CONF_REG,
    pub i2s_outfifo_push_reg: I2S_OUTFIFO_PUSH_REG,
    pub i2s_infifo_pop_reg: I2S_INFIFO_POP_REG,
    pub i2s_lc_state0_reg: I2S_LC_STATE0_REG,
    pub i2s_lc_state1_reg: I2S_LC_STATE1_REG,
    pub i2s_lc_hung_conf_reg: I2S_LC_HUNG_CONF_REG,
    pub i2s_cvsd_conf0_reg: I2S_CVSD_CONF0_REG,
    pub i2s_cvsd_conf1_reg: I2S_CVSD_CONF1_REG,
    pub i2s_cvsd_conf2_reg: I2S_CVSD_CONF2_REG,
    pub i2s_plc_conf0_reg: I2S_PLC_CONF0_REG,
    pub i2s_plc_conf1_reg: I2S_PLC_CONF1_REG,
    pub i2s_plc_conf2_reg: I2S_PLC_CONF2_REG,
    pub i2s_esco_conf0_reg: I2S_ESCO_CONF0_REG,
    pub i2s_sco_conf0_reg: I2S_SCO_CONF0_REG,
    pub i2s_conf1_reg: I2S_CONF1_REG,
    pub i2s_pd_conf_reg: I2S_PD_CONF_REG,
    pub i2s_conf2_reg: I2S_CONF2_REG,
    pub i2s_clkm_conf_reg: I2S_CLKM_CONF_REG,
    pub i2s_sample_rate_conf_reg: I2S_SAMPLE_RATE_CONF_REG,
    pub i2s_pdm_conf_reg: I2S_PDM_CONF_REG,
    pub i2s_pdm_freq_conf_reg: I2S_PDM_FREQ_CONF_REG,
    pub i2s_state_reg: I2S_STATE_REG,
    pub i2s_date_reg: I2S_DATE_REG,
    // some fields omitted
}

Register block

Fields

i2s_conf_reg: I2S_CONF_REG

0x08 - I2S_CONF_REG(i)

i2s_int_raw_reg: I2S_INT_RAW_REG

0x0c - I2S_INT_RAW_REG(i)

i2s_int_st_reg: I2S_INT_ST_REG

0x10 - I2S_INT_ST_REG(i)

i2s_int_ena_reg: I2S_INT_ENA_REG

0x14 - I2S_INT_ENA_REG(i)

i2s_int_clr_reg: I2S_INT_CLR_REG

0x18 - I2S_INT_CLR_REG(i)

i2s_timing_reg: I2S_TIMING_REG

0x1c - I2S_TIMING_REG(i)

i2s_fifo_conf_reg: I2S_FIFO_CONF_REG

0x20 - I2S_FIFO_CONF_REG(i)

i2s_rxeof_num_reg: I2S_RXEOF_NUM_REG

0x24 - I2S_RXEOF_NUM_REG(i)

i2s_conf_sigle_data_reg: I2S_CONF_SIGLE_DATA_REG

0x28 - I2S_CONF_SIGLE_DATA_REG(i)

i2s_conf_chan_reg: I2S_CONF_CHAN_REG

0x2c - I2S_CONF_CHAN_REG(i)

i2s_out_link_reg: I2S_OUT_LINK_REG

0x30 - I2S_OUT_LINK_REG(i)

i2s_in_link_reg: I2S_IN_LINK_REG

0x34 - I2S_IN_LINK_REG(i)

i2s_out_eof_des_addr_reg: I2S_OUT_EOF_DES_ADDR_REG

0x38 - I2S_OUT_EOF_DES_ADDR_REG(i)

i2s_in_eof_des_addr_reg: I2S_IN_EOF_DES_ADDR_REG

0x3c - I2S_IN_EOF_DES_ADDR_REG(i)

i2s_out_eof_bfr_des_addr_reg: I2S_OUT_EOF_BFR_DES_ADDR_REG

0x40 - I2S_OUT_EOF_BFR_DES_ADDR_REG(i)

i2s_ahb_test_reg: I2S_AHB_TEST_REG

0x44 - I2S_AHB_TEST_REG(i)

i2s_inlink_dscr_reg: I2S_INLINK_DSCR_REG

0x48 - I2S_INLINK_DSCR_REG(i)

i2s_inlink_dscr_bf0_reg: I2S_INLINK_DSCR_BF0_REG

0x4c - I2S_INLINK_DSCR_BF0_REG(i)

i2s_inlink_dscr_bf1_reg: I2S_INLINK_DSCR_BF1_REG

0x50 - I2S_INLINK_DSCR_BF1_REG(i)

i2s_outlink_dscr_reg: I2S_OUTLINK_DSCR_REG

0x54 - I2S_OUTLINK_DSCR_REG(i)

i2s_outlink_dscr_bf0_reg: I2S_OUTLINK_DSCR_BF0_REG

0x58 - I2S_OUTLINK_DSCR_BF0_REG(i)

i2s_outlink_dscr_bf1_reg: I2S_OUTLINK_DSCR_BF1_REG

0x5c - I2S_OUTLINK_DSCR_BF1_REG(i)

i2s_lc_conf_reg: I2S_LC_CONF_REG

0x60 - I2S_LC_CONF_REG(i)

i2s_outfifo_push_reg: I2S_OUTFIFO_PUSH_REG

0x64 - I2S_OUTFIFO_PUSH_REG(i)

i2s_infifo_pop_reg: I2S_INFIFO_POP_REG

0x68 - I2S_INFIFO_POP_REG(i)

i2s_lc_state0_reg: I2S_LC_STATE0_REG

0x6c - I2S_LC_STATE0_REG(i)

i2s_lc_state1_reg: I2S_LC_STATE1_REG

0x70 - I2S_LC_STATE1_REG(i)

i2s_lc_hung_conf_reg: I2S_LC_HUNG_CONF_REG

0x74 - I2S_LC_HUNG_CONF_REG(i)

i2s_cvsd_conf0_reg: I2S_CVSD_CONF0_REG

0x80 - I2S_CVSD_CONF0_REG(i)

i2s_cvsd_conf1_reg: I2S_CVSD_CONF1_REG

0x84 - I2S_CVSD_CONF1_REG(i)

i2s_cvsd_conf2_reg: I2S_CVSD_CONF2_REG

0x88 - I2S_CVSD_CONF2_REG(i)

i2s_plc_conf0_reg: I2S_PLC_CONF0_REG

0x8c - I2S_PLC_CONF0_REG(i)

i2s_plc_conf1_reg: I2S_PLC_CONF1_REG

0x90 - I2S_PLC_CONF1_REG(i)

i2s_plc_conf2_reg: I2S_PLC_CONF2_REG

0x94 - I2S_PLC_CONF2_REG(i)

i2s_esco_conf0_reg: I2S_ESCO_CONF0_REG

0x98 - I2S_ESCO_CONF0_REG(i)

i2s_sco_conf0_reg: I2S_SCO_CONF0_REG

0x9c - I2S_SCO_CONF0_REG(i)

i2s_conf1_reg: I2S_CONF1_REG

0xa0 - I2S_CONF1_REG(i)

i2s_pd_conf_reg: I2S_PD_CONF_REG

0xa4 - I2S_PD_CONF_REG(i)

i2s_conf2_reg: I2S_CONF2_REG

0xa8 - I2S_CONF2_REG(i)

i2s_clkm_conf_reg: I2S_CLKM_CONF_REG

0xac - I2S_CLKM_CONF_REG(i)

i2s_sample_rate_conf_reg: I2S_SAMPLE_RATE_CONF_REG

0xb0 - I2S_SAMPLE_RATE_CONF_REG(i)

i2s_pdm_conf_reg: I2S_PDM_CONF_REG

0xb4 - I2S_PDM_CONF_REG(i)

i2s_pdm_freq_conf_reg: I2S_PDM_FREQ_CONF_REG

0xb8 - I2S_PDM_FREQ_CONF_REG(i)

i2s_state_reg: I2S_STATE_REG

0xbc - I2S_STATE_REG(i)

i2s_date_reg: I2S_DATE_REG

0xfc - I2S_DATE_REG(i)

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