[−][src]Type Definition esp32::dport::dport_cache_ia_int_en_reg::R
type R = R<u32, DPORT_CACHE_IA_INT_EN_REG>;
Reader of register DPORT_CACHE_IA_INT_EN_REG
Methods
impl R[src]
pub fn dport_cache_ia_int_en(&self) -> DPORT_CACHE_IA_INT_EN_R[src]
Bits 0:27 - Interrupt enable bits for various invalid cache access reasons
pub fn dport_cache_ia_int_pro_opposite(
&self
) -> DPORT_CACHE_IA_INT_PRO_OPPOSITE_R[src]
&self
) -> DPORT_CACHE_IA_INT_PRO_OPPOSITE_R
Bit 19 - PRO CPU invalid access to APP CPU cache when cache disabled
pub fn dport_cache_ia_int_pro_dram1(&self) -> DPORT_CACHE_IA_INT_PRO_DRAM1_R[src]
Bit 18 - PRO CPU invalid access to DRAM1 when cache is disabled
pub fn dport_cache_ia_int_pro_irom0(&self) -> DPORT_CACHE_IA_INT_PRO_IROM0_R[src]
Bit 17 - PRO CPU invalid access to IROM0 when cache is disabled
pub fn dport_cache_ia_int_pro_iram1(&self) -> DPORT_CACHE_IA_INT_PRO_IRAM1_R[src]
Bit 16 - PRO CPU invalid access to IRAM1 when cache is disabled
pub fn dport_cache_ia_int_pro_iram0(&self) -> DPORT_CACHE_IA_INT_PRO_IRAM0_R[src]
Bit 15 - PRO CPU invalid access to IRAM0 when cache is disabled
pub fn dport_cache_ia_int_pro_drom0(&self) -> DPORT_CACHE_IA_INT_PRO_DROM0_R[src]
Bit 14 - PRO CPU invalid access to DROM0 when cache is disabled
pub fn dport_cache_ia_int_app_opposite(
&self
) -> DPORT_CACHE_IA_INT_APP_OPPOSITE_R[src]
&self
) -> DPORT_CACHE_IA_INT_APP_OPPOSITE_R
Bit 5 - APP CPU invalid access to APP CPU cache when cache disabled
pub fn dport_cache_ia_int_app_irom0(&self) -> DPORT_CACHE_IA_INT_APP_IROM0_R[src]
Bit 3 - APP CPU invalid access to IROM0 when cache is disabled
pub fn dport_cache_ia_int_app_iram1(&self) -> DPORT_CACHE_IA_INT_APP_IRAM1_R[src]
Bit 2 - APP CPU invalid access to IRAM1 when cache is disabled
pub fn dport_cache_ia_int_app_iram0(&self) -> DPORT_CACHE_IA_INT_APP_IRAM0_R[src]
Bit 1 - APP CPU invalid access to IRAM0 when cache is disabled
pub fn dport_cache_ia_int_app_drom0(&self) -> DPORT_CACHE_IA_INT_APP_DROM0_R[src]
Bit 0 - APP CPU invalid access to DROM0 when cache is disabled