Type Definition esp32::apb_ctrl::apb_ctrl_apb_saradc_ctrl_reg::W

type W = W<u32, APB_CTRL_APB_SARADC_CTRL_REG>;

Writer for register APB_CTRL_APB_SARADC_CTRL_REG

Methods

impl W

pub fn apb_ctrl_saradc_data_to_i2s(&mut self) -> APB_CTRL_SARADC_DATA_TO_I2S_W

Bit 26 - 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix

pub fn apb_ctrl_saradc_data_sar_sel(&mut self) -> APB_CTRL_SARADC_DATA_SAR_SEL_W

Bit 25 - 1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.

pub fn apb_ctrl_saradc_sar2_patt_p_clear(
    &mut self
) -> APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_W

Bit 24 - clear the pointer of pattern table for DIG ADC2 CTRL

pub fn apb_ctrl_saradc_sar1_patt_p_clear(
    &mut self
) -> APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_W

Bit 23 - clear the pointer of pattern table for DIG ADC1 CTRL

pub fn apb_ctrl_saradc_sar2_patt_len(
    &mut self
) -> APB_CTRL_SARADC_SAR2_PATT_LEN_W

Bits 19:22 - 0 ~ 15 means length 1 ~ 16

pub fn apb_ctrl_saradc_sar1_patt_len(
    &mut self
) -> APB_CTRL_SARADC_SAR1_PATT_LEN_W

Bits 15:18 - 0 ~ 15 means length 1 ~ 16

pub fn apb_ctrl_saradc_sar_clk_div(&mut self) -> APB_CTRL_SARADC_SAR_CLK_DIV_W

Bits 7:14 - SAR clock divider

pub fn apb_ctrl_saradc_sar_clk_gated(
    &mut self
) -> APB_CTRL_SARADC_SAR_CLK_GATED_W

Bit 6

pub fn apb_ctrl_saradc_sar_sel(&mut self) -> APB_CTRL_SARADC_SAR_SEL_W

Bit 5 - 0: SAR1 1: SAR2 only work for single SAR mode

pub fn apb_ctrl_saradc_work_mode(&mut self) -> APB_CTRL_SARADC_WORK_MODE_W

Bits 3:4 - 0: single mode 1: double mode 2: alternate mode

pub fn apb_ctrl_saradc_sar2_mux(&mut self) -> APB_CTRL_SARADC_SAR2_MUX_W

Bit 2 - 1: SAR ADC2 is controlled by DIG ADC2 CTRL 0: SAR ADC2 is controlled by PWDET CTRL

pub fn apb_ctrl_saradc_start(&mut self) -> APB_CTRL_SARADC_START_W

Bit 1

pub fn apb_ctrl_saradc_start_force(&mut self) -> APB_CTRL_SARADC_START_FORCE_W

Bit 0