Module esp32_hal::pac::spi0::pin

Expand description

Structs

This register you can read, write_with_zero, reset, write, modify. See API.

Register PIN reader

Register PIN writer

Field CK_DIS reader - 1: spi clk out disable 0: spi clk out enable

Field CK_DIS writer - 1: spi clk out disable 0: spi clk out enable

Field CK_IDLE_EDGE reader - 1: spi clk line is high when idle 0: spi clk line is low when idle

Field CK_IDLE_EDGE writer - 1: spi clk line is high when idle 0: spi clk line is low when idle

Field CS0_DIS reader - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin

Field CS0_DIS writer - SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin

Field CS1_DIS reader - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin

Field CS1_DIS writer - SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin

Field CS2_DIS reader - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin

Field CS2_DIS writer - SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin

Field CS_KEEP_ACTIVE reader - spi cs line keep low when the bit is set.

Field CS_KEEP_ACTIVE writer - spi cs line keep low when the bit is set.

Field MASTER_CK_SEL reader - In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.

Field MASTER_CK_SEL writer - In the master mode spi cs line is enable as spi clk it is combined with spi_cs0_dis spi_cs1_dis spi_cs2_dis.

Field MASTER_CS_POL reader - In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.

Field MASTER_CS_POL writer - In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol.