Module esp32_hal::pac::spi0::clock

Structs

CLOCK_SPEC

This register you can read, write_with_zero, reset, write, modify. See API.

R

Register CLOCK reader

W

Register CLOCK writer

Type Definitions

CLKCNT_H_R

Field CLKCNT_H reader - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.

CLKCNT_H_W

Field CLKCNT_H writer - In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.

CLKCNT_L_R

Field CLKCNT_L reader - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.

CLKCNT_L_W

Field CLKCNT_L writer - In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.

CLKCNT_N_R

Field CLKCNT_N reader - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)

CLKCNT_N_W

Field CLKCNT_N writer - In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)

CLKDIV_PRE_R

Field CLKDIV_PRE reader - In the master mode it is pre-divider of spi_clk.

CLKDIV_PRE_W

Field CLKDIV_PRE writer - In the master mode it is pre-divider of spi_clk.

CLK_EQU_SYSCLK_R

Field CLK_EQU_SYSCLK reader - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.

CLK_EQU_SYSCLK_W

Field CLK_EQU_SYSCLK writer - In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.