Module esp32_hal::pac::ledc::lstimer_conf
Expand description
Structs
Register
LSTIMER%s_CONF
readerRegister
LSTIMER%s_CONF
writerType Definitions
Field
DIV_NUM
reader - This register is used to configure parameter for divider in low speed timer0 the least significant eight bits represent the decimal part.Field
DIV_NUM
writer - This register is used to configure parameter for divider in low speed timer0 the least significant eight bits represent the decimal part.Field
DUTY_RES
reader - This register controls the range of the counter in low speed timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.Field
DUTY_RES
writer - This register controls the range of the counter in low speed timer0. the counter range is [0 2**reg_lstimer0_lim] the max bit width for counter is 20.Field
LIM
reader - Field
LIM
writer - Field
PARA_UP
reader - Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.Field
PARA_UP
writer - Set this bit to update reg_div_num_lstime0 and reg_lstimer0_lim.Field
PAUSE
reader - This bit is used to pause the counter in low speed timer0.Field
PAUSE
writer - This bit is used to pause the counter in low speed timer0.Field
RST
reader - This bit is used to reset low speed timer0 the counter will be 0 after reset.Field
RST
writer - This bit is used to reset low speed timer0 the counter will be 0 after reset.Field
TICK_SEL
reader - This bit is used to choose slow_clk or ref_tick for low speed timer0. 1’b1:slow_clk 0:ref_tickField
TICK_SEL
writer - This bit is used to choose slow_clk or ref_tick for low speed timer0. 1’b1:slow_clk 0:ref_tick