Module esp32_hal::interrupt[−][src]

Expand description

ESP32 specific interrupt handling

ESP32 uses 2-level interrupt handling: peripheral interrupts are mapped to cpu interrupts. This module redirects the cpu interrupts handler to registered peripheral interrupt handlers.

Interrupt handlers are defined using the Interrupt attribute. (Note that this is a distinct attribute from the one in the xtensa_lx_rt crate.)

To enable the interrupt and assign to a specific interrupt level use the enable or enable_with_priority functions. (This is in addition to enabling the interrupt in the respective peripherals.)

To have lowest latency possible you can use the Interrupt attribute from the xtensa_lx_rt crate to define low level/naked interrupt handlers. (This will override the interrupt handling offered by this crate for that specific interrupt level. This should especially be considered when using Level 7 = Non Maskable Interrupt level as these will not be turned off during interrupt::free sections.)

Note: If multiple edge triggered interrupts are assigned to the same level, it is not possible to detect which peripheral triggered the interrupt. Therefore all registered handlers will be called.

Note: Edge triggered interrupts can be lost when triggered after handling of another edge triggered interrupt has started.

Note: routines and variables in this module are stored in RAM because otherwise it may lead to exceptions when the flash is programmed or erased while the interrupt is called.