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#![no_std]
#![feature(const_fn)]
#![cfg_attr(feature = "alloc", feature(allocator_api))]
#![cfg_attr(feature = "alloc", feature(alloc_layout_extra))]
#![cfg_attr(feature = "alloc", feature(nonnull_slice_from_raw_parts))]
pub use embedded_hal as hal;
pub use esp32 as target;
extern crate esp32_hal_proc_macros as proc_macros;
pub use proc_macros::interrupt;
pub use proc_macros::ram;
pub mod analog;
pub mod clock_control;
pub mod delay;
pub mod dport;
pub mod efuse;
#[cfg(feature = "external_ram")]
pub mod external_ram;
pub mod gpio;
#[cfg(feature = "rt")]
pub mod interrupt;
pub mod prelude;
pub mod serial;
pub mod spi;
pub mod timer;
pub mod units;
#[cfg(feature = "alloc")]
pub mod alloc;
#[macro_use]
pub mod dprint;
#[cfg(feature = "mem")]
pub mod mem;
#[cfg(feature = "rt")]
#[doc(hidden)]
#[no_mangle]
pub unsafe extern "C" fn ESP32Reset() -> ! {
extern "C" {
static mut _rtc_fast_bss_start: u32;
static mut _rtc_fast_bss_end: u32;
static mut _rtc_slow_bss_start: u32;
static mut _rtc_slow_bss_end: u32;
static mut _stack_end_cpu0: u32;
}
xtensa_lx_rt::zero_bss(&mut _rtc_fast_bss_start, &mut _rtc_fast_bss_end);
xtensa_lx_rt::zero_bss(&mut _rtc_slow_bss_start, &mut _rtc_slow_bss_end);
#[cfg(feature = "external_ram")]
external_ram::init();
xtensa_lx::set_stack_pointer(&mut _stack_end_cpu0);
xtensa_lx_rt::Reset();
}
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
pub enum Core {
PRO = 0,
APP = 1,
}
pub fn get_core() -> Core {
match ((xtensa_lx::get_processor_id() >> 13) & 1) != 0 {
false => Core::PRO,
true => Core::APP,
}
}
pub fn get_other_core() -> Core {
match get_core() {
Core::PRO => Core::APP,
Core::APP => Core::PRO,
}
}