Module esp32_hal::efuse

Reading of eFuses

Structs

• Efuse
• EfuseField
  The bit field for get access to efuse data

Enums

• ChipType

Constants

• ABS_DONE_0
  [] Secure boot V1 is enabled for bootloader image
• ABS_DONE_1
  [] Secure boot V2 is enabled for bootloader image
• ADC1_TP_HIGH
  [] ADC1 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
• ADC1_TP_LOW
  [] ADC1 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
• ADC2_TP_HIGH
  [] ADC2 Two Point calibration high point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
• ADC2_TP_LOW
  [] ADC2 Two Point calibration low point. Only valid if EFUSE_RD_BLK3_PART_RESERVE
• ADC_VREF
  [] True ADC reference voltage
• BLK3_PART_RESERVE
  [] BLOCK3 partially served for ADC calibration data
• CHIP_CPU_FREQ_LOW
  [] If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the ESP32’s max CPU frequency is rated for 160MHz. 240MHz otherwise
• CHIP_CPU_FREQ_RATED
  [] If set; the ESP32’s maximum CPU frequency has been rated
• CHIP_PACKAGE
  [CHIP_VER_PKG] Chip package identifier
• CHIP_PACKAGE_4BIT
  [CHIP_VER_PKG_4BIT] Chip package identifier
• CHIP_VER_REV1
  [] bit is set to 1 for rev1 silicon
• CHIP_VER_REV2
  []
• CLK8M_FREQ
  [CK8M_FREQ] 8MHz clock freq override
• CODING_SCHEME
  [] Efuse variable block length scheme {0: “NONE (BLK1-3 len=256 bits)”; 1: “3/4 (BLK1-3 len=192 bits)”; 2: “REPEAT (BLK1-3 len=128 bits) not supported”; 3: “NONE (BLK1-3 len=256 bits)”}
• CONSOLE_DEBUG_DISABLE
  [] Disable ROM BASIC interpreter fallback
• CUSTOM_MAC_CRC
  [MAC_CUSTOM_CRC] CRC8 for custom MAC address
• DISABLE_APP_CPU
  [CHIP_VER_DIS_APP_CPU] Disables APP CPU
• DISABLE_BT
  [CHIP_VER_DIS_BT] Disables Bluetooth
• DISABLE_DL_CACHE
  [] Disable flash cache in UART bootloader
• DISABLE_DL_DECRYPT
  [] Disable flash decryption in UART bootloader
• DISABLE_DL_ENCRYPT
  [] Disable flash encryption in UART bootloader
• DISABLE_SDIO_HOST
  []
• DIS_CACHE
  [CHIP_VER_DIS_CACHE] Disables cache
• FLASH_CRYPT_CNT
  [] Flash encryption is enabled if this field has an odd number of bits set
• FLASH_CRYPT_CONFIG
  [ENCRYPT_CONFIG] Flash encryption config (key tweak bits)
• JTAG_DISABLE
  [DISABLE_JTAG] Disable JTAG
• KEY_STATUS
  [] Usage of efuse block 3 (reserved)
• MAC_CRC
  [MAC_FACTORY_CRC] CRC8 for MAC address
• MAC_CUSTOM
  MAC_CUSTOM Custom MAC address
• MAC_FACTORY
  MAC_FACTORY MAC address
• MAC_VERSION
  [MAC_CUSTOM_VER] Version of the MAC field {1: “Custom MAC in BLOCK3”}
• RD_DIS
  [] Disable reading from BlOCK1-3
• RD_DIS_ADC1_TP_HIGH
  [] rd_dis of ADC1_TP_HIGH
• RD_DIS_ADC1_TP_LOW
  [] rd_dis of ADC1_TP_LOW
• RD_DIS_ADC2_TP_HIGH
  [] rd_dis of ADC2_TP_HIGH
• RD_DIS_ADC2_TP_LOW
  [] rd_dis of ADC2_TP_LOW
• RD_DIS_BLK3_PART_RESERVE
  [] rd_dis of BLK3_PART_RESERVE
• RD_DIS_BLOCK1
  [RD_DIS.ENCRYPT_FLASH_KEY RD_DIS.BLK1] rd_dis of BLOCK1
• RD_DIS_BLOCK2
  [RD_DIS.SECURE_BOOT_KEY RD_DIS.BLK2] rd_dis of BLOCK2
• RD_DIS_BLOCK3
  [RD_DIS.BLK3] rd_dis of BLOCK3
• RD_DIS_CODING_SCHEME
  [] rd_dis of CODING_SCHEME
• RD_DIS_CUSTOM_MAC
  [RD_DIS.MAC_CUSTOM] rd_dis of CUSTOM_MAC
• RD_DIS_CUSTOM_MAC_CRC
  [RD_DIS.MAC_CUSTOM_CRC] rd_dis of CUSTOM_MAC_CRC
• RD_DIS_FLASH_CRYPT_CONFIG
  [RD_DIS.ENCRYPT_CONFIG] rd_dis of FLASH_CRYPT_CONFIG
• RD_DIS_KEY_STATUS
  [] rd_dis of KEY_STATUS
• RD_DIS_MAC_VERSION
  [RD_DIS.MAC_CUSTOM_VER] rd_dis of MAC_VERSION
• RD_DIS_SECURE_VERSION
  [] rd_dis of SECURE_VERSION
• SECURE_VERSION
  [] Secure version for anti-rollback
• SPI_PAD_CONFIG_CLK
  [] Override SD_CLK pad (GPIO6/SPICLK)
• SPI_PAD_CONFIG_CS0
  [] Override SD_CMD pad (GPIO11/SPICS0)
• SPI_PAD_CONFIG_D
  [] Override SD_DATA_1 pad (GPIO8/SPID)
• SPI_PAD_CONFIG_HD
  [] read for SPI_pad_config_hd
• SPI_PAD_CONFIG_Q
  [] Override SD_DATA_0 pad (GPIO7/SPIQ)
• UART_DOWNLOAD_DIS
  [] Disable UART download mode. Valid for ESP32 V3 and newer; only
• VOL_LEVEL_HP_INV
  [] This field stores the voltage level for CPU to run at 240 MHz; or for flash/PSRAM to run at 80 MHz.0x0: level 7; 0x1: level 6; 0x2: level 5; 0x3: level 4. (RO)
• WAFER_VERSION_MINOR
  []
• WR_DIS
  [] Efuse write disable mask
• WR_DIS_ABS_DONE_0
  [] wr_dis of ABS_DONE_0
• WR_DIS_ABS_DONE_1
  [] wr_dis of ABS_DONE_1
• WR_DIS_ADC1_TP_HIGH
  [] wr_dis of ADC1_TP_HIGH
• WR_DIS_ADC1_TP_LOW
  [] wr_dis of ADC1_TP_LOW
• WR_DIS_ADC2_TP_HIGH
  [] wr_dis of ADC2_TP_HIGH
• WR_DIS_ADC2_TP_LOW
  [] wr_dis of ADC2_TP_LOW
• WR_DIS_ADC_VREF
  [] wr_dis of ADC_VREF
• WR_DIS_BLK3_PART_RESERVE
  [] wr_dis of BLK3_PART_RESERVE
• WR_DIS_BLOCK1
  [WR_DIS.ENCRYPT_FLASH_KEY WR_DIS.BLK1] wr_dis of BLOCK1
• WR_DIS_BLOCK2
  [WR_DIS.SECURE_BOOT_KEY WR_DIS.BLK2] wr_dis of BLOCK2
• WR_DIS_BLOCK3
  [WR_DIS.BLK3] wr_dis of BLOCK3
• WR_DIS_CLK8M_FREQ
  [WR_DIS.CK8M_FREQ] wr_dis of CLK8M_FREQ
• WR_DIS_CODING_SCHEME
  [] wr_dis of CODING_SCHEME
• WR_DIS_CONSOLE_DEBUG_DISABLE
  [] wr_dis of CONSOLE_DEBUG_DISABLE
• WR_DIS_CUSTOM_MAC
  [WR_DIS.MAC_CUSTOM] wr_dis of CUSTOM_MAC
• WR_DIS_CUSTOM_MAC_CRC
  [WR_DIS.MAC_CUSTOM_CRC] wr_dis of CUSTOM_MAC_CRC
• WR_DIS_DISABLE_APP_CPU
  [WR_DIS.CHIP_VER_DIS_APP_CPU] wr_dis of DISABLE_APP_CPU
• WR_DIS_DISABLE_BT
  [WR_DIS.CHIP_VER_DIS_BT] wr_dis of DISABLE_BT
• WR_DIS_DISABLE_DL_CACHE
  [] wr_dis of DISABLE_DL_CACHE
• WR_DIS_DISABLE_DL_DECRYPT
  [] wr_dis of DISABLE_DL_DECRYPT
• WR_DIS_DISABLE_DL_ENCRYPT
  [] wr_dis of DISABLE_DL_ENCRYPT
• WR_DIS_DIS_CACHE
  [WR_DIS.CHIP_VER_DIS_CACHE] wr_dis of DIS_CACHE
• WR_DIS_FLASH_CRYPT_CNT
  [] wr_dis of FLASH_CRYPT_CNT
• WR_DIS_FLASH_CRYPT_CONFIG
  [WR_DIS.ENCRYPT_CONFIG] wr_dis of FLASH_CRYPT_CONFIG
• WR_DIS_JTAG_DISABLE
  [WR_DIS.DISABLE_JTAG] wr_dis of JTAG_DISABLE
• WR_DIS_KEY_STATUS
  [] wr_dis of KEY_STATUS
• WR_DIS_MAC
  [WR_DIS.MAC_FACTORY] wr_dis of MAC
• WR_DIS_MAC_CRC
  [WR_DIS.MAC_FACTORY_CRC] wr_dis of MAC_CRC
• WR_DIS_MAC_VERSION
  [WR_DIS.MAC_CUSTOM_VER] wr_dis of MAC_VERSION
• WR_DIS_RD_DIS
  [WR_DIS.EFUSE_RD_DISABLE] wr_dis of RD_DIS
• WR_DIS_SECURE_VERSION
  [] wr_dis of SECURE_VERSION
• WR_DIS_SPI_PAD_CONFIG_CLK
  [] wr_dis of SPI_PAD_CONFIG_CLK
• WR_DIS_SPI_PAD_CONFIG_CS0
  [] wr_dis of SPI_PAD_CONFIG_CS0
• WR_DIS_SPI_PAD_CONFIG_D
  [] wr_dis of SPI_PAD_CONFIG_D
• WR_DIS_SPI_PAD_CONFIG_Q
  [] wr_dis of SPI_PAD_CONFIG_Q
• WR_DIS_UART_DOWNLOAD_DIS
  [] wr_dis of UART_DOWNLOAD_DIS
• WR_DIS_VOL_LEVEL_HP_INV
  [] wr_dis of VOL_LEVEL_HP_INV
• WR_DIS_WR_DIS
  [] wr_dis of WR_DIS
• WR_DIS_XPD_SDIO_FORCE
  [WR_DIS.SDIO_FORCE] wr_dis of XPD_SDIO_FORCE
• WR_DIS_XPD_SDIO_REG
  [] wr_dis of XPD_SDIO_REG
• WR_DIS_XPD_SDIO_TIEH
  [WR_DIS.SDIO_TIEH] wr_dis of XPD_SDIO_TIEH
• XPD_SDIO_FORCE
  [SDIO_FORCE] Ignore MTDI pin (GPIO12) for VDD_SDIO on reset
• XPD_SDIO_REG
  [] read for XPD_SDIO_REG
• XPD_SDIO_TIEH
  [SDIO_TIEH] If XPD_SDIO_FORCE & XPD_SDIO_REG {1: “3.3V”; 0: “1.8V”}