Module clock 

APLL 50 MHz clock configuration and GPIO clock output/input setup.

The ESP32 EMAC RMII interface requires a 50 MHz reference clock. It can be generated internally by the Audio PLL (APLL) or supplied externally from the PHY crystal oscillator.

Internal APLL mode

1. configure_apll_50mhz powers up APLL and programs its coefficients via ROM I2C to produce 50 MHz from the 40 MHz XTAL.
2. configure_emac_clk_out sets up a GPIO (0, 16, or 17) as clock output via IO_MUX function 5 so the PHY receives 50 MHz.

The EMAC_EXT clock path registers (int_en, clk_sel, clk_en) are configured separately by Emac::init via configure_phy_interface() and enable_ext_clocks().

External clock mode

configure_emac_clk_in sets up a GPIO as clock input via IO_MUX. The EMAC_EXT registers for external mode are handled by Emac::init.

APLL/WiFi conflict

APLL cannot coexist with WiFi/BT (ESP32 errata CLK-3.22). Use external clock when Ethernet + WiFi is needed.

ROM I2C details

esp-hal does not yet expose APLL configuration (its soc/esp32/clocks.rs has todo!()). We use the ROM I2C functions directly:

• APLL I2C block ID: 0x6D, host ID: 3 (verified on hardware).
• ANA_CONF register (0x3FF4_8030): bit 24 = PU, bit 23 = PD.

Structs

ApllCoefficients

SDM coefficients for the ESP32 APLL.

Functions

configure_apll_50mhz

Configure ESP32 APLL to output 50 MHz for EMAC RMII clock, using SDM coefficients chosen for the on-board crystal.

configure_emac_clk_in

Configure a GPIO as EMAC external 50 MHz clock input via IO_MUX.

configure_emac_clk_out

Configure a GPIO as EMAC 50 MHz RMII clock output via IO_MUX function 5.