eos_s3/aip/
rtc_ctrl_2.rs

1#[doc = "Register `RTC_CTRL_2` reader"]
2pub struct R(crate::R<RTC_CTRL_2_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<RTC_CTRL_2_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<RTC_CTRL_2_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<RTC_CTRL_2_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `RTC_CTRL_2` writer"]
17pub struct W(crate::W<RTC_CTRL_2_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<RTC_CTRL_2_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<RTC_CTRL_2_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<RTC_CTRL_2_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `clke` reader - 1'b1 RTC Clock Output Enable (No SYNC Needed)"]
38pub struct CLKE_R(crate::FieldReader<bool, bool>);
39impl CLKE_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: bool) -> Self {
42        CLKE_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for CLKE_R {
46    type Target = crate::FieldReader<bool, bool>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `clke` writer - 1'b1 RTC Clock Output Enable (No SYNC Needed)"]
53pub struct CLKE_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> CLKE_W<'a> {
57    #[doc = r"Sets the field bit"]
58    #[inline(always)]
59    pub fn set_bit(self) -> &'a mut W {
60        self.bit(true)
61    }
62    #[doc = r"Clears the field bit"]
63    #[inline(always)]
64    pub fn clear_bit(self) -> &'a mut W {
65        self.bit(false)
66    }
67    #[doc = r"Writes raw bits to the field"]
68    #[inline(always)]
69    pub fn bit(self, value: bool) -> &'a mut W {
70        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
71        self.w
72    }
73}
74#[doc = "Field `byp16k` reader - Changes internal clock division for 16384 Hz bypass compatibility -- 1'b0 : xtal is 32KHz - 1'b1 : xtal is 16KHz"]
75pub struct BYP16K_R(crate::FieldReader<bool, bool>);
76impl BYP16K_R {
77    #[inline(always)]
78    pub(crate) fn new(bits: bool) -> Self {
79        BYP16K_R(crate::FieldReader::new(bits))
80    }
81}
82impl core::ops::Deref for BYP16K_R {
83    type Target = crate::FieldReader<bool, bool>;
84    #[inline(always)]
85    fn deref(&self) -> &Self::Target {
86        &self.0
87    }
88}
89#[doc = "Field `byp16k` writer - Changes internal clock division for 16384 Hz bypass compatibility -- 1'b0 : xtal is 32KHz - 1'b1 : xtal is 16KHz"]
90pub struct BYP16K_W<'a> {
91    w: &'a mut W,
92}
93impl<'a> BYP16K_W<'a> {
94    #[doc = r"Sets the field bit"]
95    #[inline(always)]
96    pub fn set_bit(self) -> &'a mut W {
97        self.bit(true)
98    }
99    #[doc = r"Clears the field bit"]
100    #[inline(always)]
101    pub fn clear_bit(self) -> &'a mut W {
102        self.bit(false)
103    }
104    #[doc = r"Writes raw bits to the field"]
105    #[inline(always)]
106    pub fn bit(self, value: bool) -> &'a mut W {
107        self.w.bits =
108            (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
109        self.w
110    }
111}
112#[doc = "Field `test_ctrl` reader - RTC test\\[4:3\\]
113control for rtc bypass mode -- 0: test\\[4:3\\]
114will be forced to 2'b11 when pad8 is strapped to 1, and forced to 2'b00 when pad8 is strapped to 0 , 1: normal mode; test\\[4:0\\]
115controlled from 0x1C"]
116pub struct TEST_CTRL_R(crate::FieldReader<bool, bool>);
117impl TEST_CTRL_R {
118    #[inline(always)]
119    pub(crate) fn new(bits: bool) -> Self {
120        TEST_CTRL_R(crate::FieldReader::new(bits))
121    }
122}
123impl core::ops::Deref for TEST_CTRL_R {
124    type Target = crate::FieldReader<bool, bool>;
125    #[inline(always)]
126    fn deref(&self) -> &Self::Target {
127        &self.0
128    }
129}
130#[doc = "Field `test_ctrl` writer - RTC test\\[4:3\\]
131control for rtc bypass mode -- 0: test\\[4:3\\]
132will be forced to 2'b11 when pad8 is strapped to 1, and forced to 2'b00 when pad8 is strapped to 0 , 1: normal mode; test\\[4:0\\]
133controlled from 0x1C"]
134pub struct TEST_CTRL_W<'a> {
135    w: &'a mut W,
136}
137impl<'a> TEST_CTRL_W<'a> {
138    #[doc = r"Sets the field bit"]
139    #[inline(always)]
140    pub fn set_bit(self) -> &'a mut W {
141        self.bit(true)
142    }
143    #[doc = r"Clears the field bit"]
144    #[inline(always)]
145    pub fn clear_bit(self) -> &'a mut W {
146        self.bit(false)
147    }
148    #[doc = r"Writes raw bits to the field"]
149    #[inline(always)]
150    pub fn bit(self, value: bool) -> &'a mut W {
151        self.w.bits =
152            (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
153        self.w
154    }
155}
156impl R {
157    #[doc = "Bit 0 - 1'b1 RTC Clock Output Enable (No SYNC Needed)"]
158    #[inline(always)]
159    pub fn clke(&self) -> CLKE_R {
160        CLKE_R::new((self.bits & 0x01) != 0)
161    }
162    #[doc = "Bit 1 - Changes internal clock division for 16384 Hz bypass compatibility -- 1'b0 : xtal is 32KHz - 1'b1 : xtal is 16KHz"]
163    #[inline(always)]
164    pub fn byp16k(&self) -> BYP16K_R {
165        BYP16K_R::new(((self.bits >> 1) & 0x01) != 0)
166    }
167    #[doc = "Bit 2 - RTC test\\[4:3\\]
168control for rtc bypass mode -- 0: test\\[4:3\\]
169will be forced to 2'b11 when pad8 is strapped to 1, and forced to 2'b00 when pad8 is strapped to 0 , 1: normal mode; test\\[4:0\\]
170controlled from 0x1C"]
171    #[inline(always)]
172    pub fn test_ctrl(&self) -> TEST_CTRL_R {
173        TEST_CTRL_R::new(((self.bits >> 2) & 0x01) != 0)
174    }
175}
176impl W {
177    #[doc = "Bit 0 - 1'b1 RTC Clock Output Enable (No SYNC Needed)"]
178    #[inline(always)]
179    pub fn clke(&mut self) -> CLKE_W {
180        CLKE_W { w: self }
181    }
182    #[doc = "Bit 1 - Changes internal clock division for 16384 Hz bypass compatibility -- 1'b0 : xtal is 32KHz - 1'b1 : xtal is 16KHz"]
183    #[inline(always)]
184    pub fn byp16k(&mut self) -> BYP16K_W {
185        BYP16K_W { w: self }
186    }
187    #[doc = "Bit 2 - RTC test\\[4:3\\]
188control for rtc bypass mode -- 0: test\\[4:3\\]
189will be forced to 2'b11 when pad8 is strapped to 1, and forced to 2'b00 when pad8 is strapped to 0 , 1: normal mode; test\\[4:0\\]
190controlled from 0x1C"]
191    #[inline(always)]
192    pub fn test_ctrl(&mut self) -> TEST_CTRL_W {
193        TEST_CTRL_W { w: self }
194    }
195    #[doc = "Writes raw bits to the register."]
196    #[inline(always)]
197    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
198        self.0.bits(bits);
199        self
200    }
201}
202#[doc = "RTC control register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtc_ctrl_2](index.html) module"]
203pub struct RTC_CTRL_2_SPEC;
204impl crate::RegisterSpec for RTC_CTRL_2_SPEC {
205    type Ux = u32;
206}
207#[doc = "`read()` method returns [rtc_ctrl_2::R](R) reader structure"]
208impl crate::Readable for RTC_CTRL_2_SPEC {
209    type Reader = R;
210}
211#[doc = "`write(|w| ..)` method takes [rtc_ctrl_2::W](W) writer structure"]
212impl crate::Writable for RTC_CTRL_2_SPEC {
213    type Writer = W;
214}
215#[doc = "`reset()` method sets RTC_CTRL_2 to value 0x01"]
216impl crate::Resettable for RTC_CTRL_2_SPEC {
217    #[inline(always)]
218    fn reset_value() -> Self::Ux {
219        0x01
220    }
221}
eos_s3/aip/rtc_ctrl_2.rs

eos_s3/aip/
rtc_ctrl_2.rs
