eos_s3/uart/
uart_tcr.rs

1#[doc = "Register `UART_TCR` writer"]
2pub struct W(crate::W<UART_TCR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<UART_TCR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<UART_TCR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<UART_TCR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `ITEN` writer - Integration test enable."]
23pub struct ITEN_W<'a> {
24    w: &'a mut W,
25}
26impl<'a> ITEN_W<'a> {
27    #[doc = r"Sets the field bit"]
28    #[inline(always)]
29    pub fn set_bit(self) -> &'a mut W {
30        self.bit(true)
31    }
32    #[doc = r"Clears the field bit"]
33    #[inline(always)]
34    pub fn clear_bit(self) -> &'a mut W {
35        self.bit(false)
36    }
37    #[doc = r"Writes raw bits to the field"]
38    #[inline(always)]
39    pub fn bit(self, value: bool) -> &'a mut W {
40        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
41        self.w
42    }
43}
44#[doc = "Field `TESTFINFO` writer - Test FIFO enable."]
45pub struct TESTFINFO_W<'a> {
46    w: &'a mut W,
47}
48impl<'a> TESTFINFO_W<'a> {
49    #[doc = r"Sets the field bit"]
50    #[inline(always)]
51    pub fn set_bit(self) -> &'a mut W {
52        self.bit(true)
53    }
54    #[doc = r"Clears the field bit"]
55    #[inline(always)]
56    pub fn clear_bit(self) -> &'a mut W {
57        self.bit(false)
58    }
59    #[doc = r"Writes raw bits to the field"]
60    #[inline(always)]
61    pub fn bit(self, value: bool) -> &'a mut W {
62        self.w.bits =
63            (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
64        self.w
65    }
66}
67#[doc = "Field `SIRTEST` writer - Siren test enable."]
68pub struct SIRTEST_W<'a> {
69    w: &'a mut W,
70}
71impl<'a> SIRTEST_W<'a> {
72    #[doc = r"Sets the field bit"]
73    #[inline(always)]
74    pub fn set_bit(self) -> &'a mut W {
75        self.bit(true)
76    }
77    #[doc = r"Clears the field bit"]
78    #[inline(always)]
79    pub fn clear_bit(self) -> &'a mut W {
80        self.bit(false)
81    }
82    #[doc = r"Writes raw bits to the field"]
83    #[inline(always)]
84    pub fn bit(self, value: bool) -> &'a mut W {
85        self.w.bits =
86            (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
87        self.w
88    }
89}
90impl W {
91    #[doc = "Bit 0 - Integration test enable."]
92    #[inline(always)]
93    pub fn iten(&mut self) -> ITEN_W {
94        ITEN_W { w: self }
95    }
96    #[doc = "Bit 1 - Test FIFO enable."]
97    #[inline(always)]
98    pub fn testfinfo(&mut self) -> TESTFINFO_W {
99        TESTFINFO_W { w: self }
100    }
101    #[doc = "Bit 2 - Siren test enable."]
102    #[inline(always)]
103    pub fn sirtest(&mut self) -> SIRTEST_W {
104        SIRTEST_W { w: self }
105    }
106    #[doc = "Writes raw bits to the register."]
107    #[inline(always)]
108    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
109        self.0.bits(bits);
110        self
111    }
112}
113#[doc = "Test Control Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_tcr](index.html) module"]
114pub struct UART_TCR_SPEC;
115impl crate::RegisterSpec for UART_TCR_SPEC {
116    type Ux = u32;
117}
118#[doc = "`write(|w| ..)` method takes [uart_tcr::W](W) writer structure"]
119impl crate::Writable for UART_TCR_SPEC {
120    type Writer = W;
121}
122#[doc = "`reset()` method sets UART_TCR to value 0"]
123impl crate::Resettable for UART_TCR_SPEC {
124    #[inline(always)]
125    fn reset_value() -> Self::Ux {
126        0
127    }
128}
eos_s3/uart/uart_tcr.rs

eos_s3/uart/
uart_tcr.rs
