eos_s3/sdma/
dma_waitonreq_status.rs1#[doc = "Register `DMA_WAITONREQ_STATUS` reader"]
2pub struct R(crate::R<DMA_WAITONREQ_STATUS_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<DMA_WAITONREQ_STATUS_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<DMA_WAITONREQ_STATUS_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<DMA_WAITONREQ_STATUS_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Field `dma_waitonreq_status` reader - Channel wait on request status. \n \n Read as: \n \n Bit \\[C\\]
17= 0 dma_waitonreq\\[C\\]
18is LOW. \n \n Bit \\[C\\]
19= 1 dma_waitonreq\\[C\\]
20is HIGH."]
21pub struct DMA_WAITONREQ_STATUS_R(crate::FieldReader<u16, u16>);
22impl DMA_WAITONREQ_STATUS_R {
23 #[inline(always)]
24 pub(crate) fn new(bits: u16) -> Self {
25 DMA_WAITONREQ_STATUS_R(crate::FieldReader::new(bits))
26 }
27}
28impl core::ops::Deref for DMA_WAITONREQ_STATUS_R {
29 type Target = crate::FieldReader<u16, u16>;
30 #[inline(always)]
31 fn deref(&self) -> &Self::Target {
32 &self.0
33 }
34}
35impl R {
36 #[doc = "Bits 0:15 - Channel wait on request status. \n \n Read as: \n \n Bit \\[C\\]
37= 0 dma_waitonreq\\[C\\]
38is LOW. \n \n Bit \\[C\\]
39= 1 dma_waitonreq\\[C\\]
40is HIGH."]
41 #[inline(always)]
42 pub fn dma_waitonreq_status(&self) -> DMA_WAITONREQ_STATUS_R {
43 DMA_WAITONREQ_STATUS_R::new((self.bits & 0xffff) as u16)
44 }
45}
46#[doc = "Channel wait on request status\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_waitonreq_status](index.html) module"]
47pub struct DMA_WAITONREQ_STATUS_SPEC;
48impl crate::RegisterSpec for DMA_WAITONREQ_STATUS_SPEC {
49 type Ux = u32;
50}
51#[doc = "`read()` method returns [dma_waitonreq_status::R](R) reader structure"]
52impl crate::Readable for DMA_WAITONREQ_STATUS_SPEC {
53 type Reader = R;
54}
55#[doc = "`reset()` method sets DMA_WAITONREQ_STATUS to value 0"]
56impl crate::Resettable for DMA_WAITONREQ_STATUS_SPEC {
57 #[inline(always)]
58 fn reset_value() -> Self::Ux {
59 0
60 }
61}