eos_s3/sdma/
chnl_useburst_set.rs

1#[doc = "Register `CHNL_USEBURST_SET` writer"]
2pub struct W(crate::W<CHNL_USEBURST_SET_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CHNL_USEBURST_SET_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CHNL_USEBURST_SET_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CHNL_USEBURST_SET_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `chnl_useburst_clr` writer - Set the appropriate bit to enable dma_sreq\\[\\]
23to generate requests. Write as: \n \n Bit \\[C\\]
24= 0 No effect. Use the chnl_useburst_set Register to disable dma_sreq\\[\\]
25from generating requests. \n \n Bit \\[C\\]
26= 1 Enables dma_sreq\\[C\\]
27to generate DMA requests. \n\n Writing to a bit where a DMA channel is not implemented has no effect"]
28pub struct CHNL_USEBURST_CLR_W<'a> {
29    w: &'a mut W,
30}
31impl<'a> CHNL_USEBURST_CLR_W<'a> {
32    #[doc = r"Writes raw bits to the field"]
33    #[inline(always)]
34    pub unsafe fn bits(self, value: u16) -> &'a mut W {
35        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
36        self.w
37    }
38}
39impl W {
40    #[doc = "Bits 0:15 - Set the appropriate bit to enable dma_sreq\\[\\]
41to generate requests. Write as: \n \n Bit \\[C\\]
42= 0 No effect. Use the chnl_useburst_set Register to disable dma_sreq\\[\\]
43from generating requests. \n \n Bit \\[C\\]
44= 1 Enables dma_sreq\\[C\\]
45to generate DMA requests. \n\n Writing to a bit where a DMA channel is not implemented has no effect"]
46    #[inline(always)]
47    pub fn chnl_useburst_clr(&mut self) -> CHNL_USEBURST_CLR_W {
48        CHNL_USEBURST_CLR_W { w: self }
49    }
50    #[doc = "Writes raw bits to the register."]
51    #[inline(always)]
52    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
53        self.0.bits(bits);
54        self
55    }
56}
57#[doc = "Set the appropriate bit to enable dma_sreq\\[Channel\\]
58to generate requests.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_useburst_set](index.html) module"]
59pub struct CHNL_USEBURST_SET_SPEC;
60impl crate::RegisterSpec for CHNL_USEBURST_SET_SPEC {
61    type Ux = u32;
62}
63#[doc = "`write(|w| ..)` method takes [chnl_useburst_set::W](W) writer structure"]
64impl crate::Writable for CHNL_USEBURST_SET_SPEC {
65    type Writer = W;
66}
67#[doc = "`reset()` method sets CHNL_USEBURST_SET to value 0"]
68impl crate::Resettable for CHNL_USEBURST_SET_SPEC {
69    #[inline(always)]
70    fn reset_value() -> Self::Ux {
71        0
72    }
73}
eos_s3/sdma/chnl_useburst_set.rs

eos_s3/sdma/
chnl_useburst_set.rs
