eos_s3/sdma/
chnl_priority_set.rs

1#[doc = "Register `CHNL_PRIORITY_SET` writer"]
2pub struct W(crate::W<CHNL_PRIORITY_SET_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CHNL_PRIORITY_SET_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CHNL_PRIORITY_SET_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CHNL_PRIORITY_SET_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `chnl_priority_set` writer - Returns the channel priority mask status, or sets the channel priority to high. Read as: \n \n Bit \\[C\\]
23= 0 DMA channel C is using the default priority level. \n \n Bit \\[C\\]
24= 1 DMA channel C is using a high priority level. \n \n Write as: \n \n Bit \\[C\\]
25= 0 No effect. Use the chnl_priority_clr Register to set channel C to the default priority level. \n \n Bit \\[C\\]
26= 1 Channel C uses the high priority level. \n \n Writing to a bit where a DMA channel is not implemented has no effect."]
27pub struct CHNL_PRIORITY_SET_W<'a> {
28    w: &'a mut W,
29}
30impl<'a> CHNL_PRIORITY_SET_W<'a> {
31    #[doc = r"Writes raw bits to the field"]
32    #[inline(always)]
33    pub unsafe fn bits(self, value: u16) -> &'a mut W {
34        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
35        self.w
36    }
37}
38impl W {
39    #[doc = "Bits 0:15 - Returns the channel priority mask status, or sets the channel priority to high. Read as: \n \n Bit \\[C\\]
40= 0 DMA channel C is using the default priority level. \n \n Bit \\[C\\]
41= 1 DMA channel C is using a high priority level. \n \n Write as: \n \n Bit \\[C\\]
42= 0 No effect. Use the chnl_priority_clr Register to set channel C to the default priority level. \n \n Bit \\[C\\]
43= 1 Channel C uses the high priority level. \n \n Writing to a bit where a DMA channel is not implemented has no effect."]
44    #[inline(always)]
45    pub fn chnl_priority_set(&mut self) -> CHNL_PRIORITY_SET_W {
46        CHNL_PRIORITY_SET_W { w: self }
47    }
48    #[doc = "Writes raw bits to the register."]
49    #[inline(always)]
50    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
51        self.0.bits(bits);
52        self
53    }
54}
55#[doc = "Returns the channel priority mask status, or sets the channel priority to high.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_priority_set](index.html) module"]
56pub struct CHNL_PRIORITY_SET_SPEC;
57impl crate::RegisterSpec for CHNL_PRIORITY_SET_SPEC {
58    type Ux = u32;
59}
60#[doc = "`write(|w| ..)` method takes [chnl_priority_set::W](W) writer structure"]
61impl crate::Writable for CHNL_PRIORITY_SET_SPEC {
62    type Writer = W;
63}
64#[doc = "`reset()` method sets CHNL_PRIORITY_SET to value 0"]
65impl crate::Resettable for CHNL_PRIORITY_SET_SPEC {
66    #[inline(always)]
67    fn reset_value() -> Self::Ux {
68        0
69    }
70}
eos_s3/sdma/chnl_priority_set.rs

eos_s3/sdma/
chnl_priority_set.rs
