eos_s3/i2s_slave/
rtxdma.rs

1#[doc = "Register `RTXDMA` writer"]
2pub struct W(crate::W<RTXDMA_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<RTXDMA_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<RTXDMA_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<RTXDMA_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `RTXDMA` writer - Reset Transmitter Block DMA Register. Writing a 1 to this self-clearing register resets the TXDMA register mid-cycle to point to the lowest enabled Transmit channel. NOTE: This register has no effect in the middle of a stereo pair write (such as,when left stereo data has been written but not right stereo data)"]
23pub struct RTXDMA_W<'a> {
24    w: &'a mut W,
25}
26impl<'a> RTXDMA_W<'a> {
27    #[doc = r"Sets the field bit"]
28    #[inline(always)]
29    pub fn set_bit(self) -> &'a mut W {
30        self.bit(true)
31    }
32    #[doc = r"Clears the field bit"]
33    #[inline(always)]
34    pub fn clear_bit(self) -> &'a mut W {
35        self.bit(false)
36    }
37    #[doc = r"Writes raw bits to the field"]
38    #[inline(always)]
39    pub fn bit(self, value: bool) -> &'a mut W {
40        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
41        self.w
42    }
43}
44impl W {
45    #[doc = "Bit 0 - Reset Transmitter Block DMA Register. Writing a 1 to this self-clearing register resets the TXDMA register mid-cycle to point to the lowest enabled Transmit channel. NOTE: This register has no effect in the middle of a stereo pair write (such as,when left stereo data has been written but not right stereo data)"]
46    #[inline(always)]
47    pub fn rtxdma(&mut self) -> RTXDMA_W {
48        RTXDMA_W { w: self }
49    }
50    #[doc = "Writes raw bits to the register."]
51    #[inline(always)]
52    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
53        self.0.bits(bits);
54        self
55    }
56}
57#[doc = "Reset Transmitter Block DMA Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rtxdma](index.html) module"]
58pub struct RTXDMA_SPEC;
59impl crate::RegisterSpec for RTXDMA_SPEC {
60    type Ux = u32;
61}
62#[doc = "`write(|w| ..)` method takes [rtxdma::W](W) writer structure"]
63impl crate::Writable for RTXDMA_SPEC {
64    type Writer = W;
65}
66#[doc = "`reset()` method sets RTXDMA to value 0"]
67impl crate::Resettable for RTXDMA_SPEC {
68    #[inline(always)]
69    fn reset_value() -> Self::Ux {
70        0
71    }
72}
eos_s3/i2s_slave/rtxdma.rs

eos_s3/i2s_slave/
rtxdma.rs
