eos_s3/i2s_slave/
lthr0.rs

1#[doc = "Register `LTHR0` writer"]
2pub struct W(crate::W<LTHR0_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<LTHR0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<LTHR0_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<LTHR0_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `LTHR0` writer - The left stereo data to be transmitted serially through the transmit channel output (sdox) is written through this register. Writing is a two-stage process: (1) A write to this register passes the left stereo sample to the transmitter. (2) This MUST be followed by writing the right stereo sample to the RTHRx register. Data should only be written to the FIFO when it is not full. Any attempt to write to a full FIFO results in that data being lost and an overrun interrupt being generated."]
23pub struct LTHR0_W<'a> {
24    w: &'a mut W,
25}
26impl<'a> LTHR0_W<'a> {
27    #[doc = r"Writes raw bits to the field"]
28    #[inline(always)]
29    pub unsafe fn bits(self, value: u32) -> &'a mut W {
30        self.w.bits = value as u32;
31        self.w
32    }
33}
34impl W {
35    #[doc = "Bits 0:31 - The left stereo data to be transmitted serially through the transmit channel output (sdox) is written through this register. Writing is a two-stage process: (1) A write to this register passes the left stereo sample to the transmitter. (2) This MUST be followed by writing the right stereo sample to the RTHRx register. Data should only be written to the FIFO when it is not full. Any attempt to write to a full FIFO results in that data being lost and an overrun interrupt being generated."]
36    #[inline(always)]
37    pub fn lthr0(&mut self) -> LTHR0_W {
38        LTHR0_W { w: self }
39    }
40    #[doc = "Writes raw bits to the register."]
41    #[inline(always)]
42    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
43        self.0.bits(bits);
44        self
45    }
46}
47#[doc = "Left Transmit Holding Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [lthr0](index.html) module"]
48pub struct LTHR0_SPEC;
49impl crate::RegisterSpec for LTHR0_SPEC {
50    type Ux = u32;
51}
52#[doc = "`write(|w| ..)` method takes [lthr0::W](W) writer structure"]
53impl crate::Writable for LTHR0_SPEC {
54    type Writer = W;
55}
56#[doc = "`reset()` method sets LTHR0 to value 0"]
57impl crate::Resettable for LTHR0_SPEC {
58    #[inline(always)]
59    fn reset_value() -> Self::Ux {
60        0
61    }
62}
eos_s3/i2s_slave/lthr0.rs

eos_s3/i2s_slave/
lthr0.rs
