eos_s3/sdma/
chnl_enable_set.rs

1#[doc = "Register `CHNL_ENABLE_SET` reader"]
2pub struct R(crate::R<CHNL_ENABLE_SET_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CHNL_ENABLE_SET_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CHNL_ENABLE_SET_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CHNL_ENABLE_SET_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CHNL_ENABLE_SET` writer"]
17pub struct W(crate::W<CHNL_ENABLE_SET_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CHNL_ENABLE_SET_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CHNL_ENABLE_SET_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CHNL_ENABLE_SET_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `chnl_enable_set` reader - Returns the enable status of the channels, or enables the corresponding channels. Read as: \n \n Bit \\[C\\]
38= 0 Channel C is disabled. \n \n Bit \\[C\\]
39= 1 Channel C is enabled. \n \n Write as: \n \n Bit \\[C\\]
40= 0 No effect. Use the chnl_enable_clr Register to disable a channel. \n \n Bit \\[C\\]
41= 1 Enables channel C. \n \n Writing to a bit where a DMA channel is not implemented has no effect."]
42pub struct CHNL_ENABLE_SET_R(crate::FieldReader<u16, u16>);
43impl CHNL_ENABLE_SET_R {
44    #[inline(always)]
45    pub(crate) fn new(bits: u16) -> Self {
46        CHNL_ENABLE_SET_R(crate::FieldReader::new(bits))
47    }
48}
49impl core::ops::Deref for CHNL_ENABLE_SET_R {
50    type Target = crate::FieldReader<u16, u16>;
51    #[inline(always)]
52    fn deref(&self) -> &Self::Target {
53        &self.0
54    }
55}
56#[doc = "Field `chnl_enable_set` writer - Returns the enable status of the channels, or enables the corresponding channels. Read as: \n \n Bit \\[C\\]
57= 0 Channel C is disabled. \n \n Bit \\[C\\]
58= 1 Channel C is enabled. \n \n Write as: \n \n Bit \\[C\\]
59= 0 No effect. Use the chnl_enable_clr Register to disable a channel. \n \n Bit \\[C\\]
60= 1 Enables channel C. \n \n Writing to a bit where a DMA channel is not implemented has no effect."]
61pub struct CHNL_ENABLE_SET_W<'a> {
62    w: &'a mut W,
63}
64impl<'a> CHNL_ENABLE_SET_W<'a> {
65    #[doc = r"Writes raw bits to the field"]
66    #[inline(always)]
67    pub unsafe fn bits(self, value: u16) -> &'a mut W {
68        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
69        self.w
70    }
71}
72impl R {
73    #[doc = "Bits 0:15 - Returns the enable status of the channels, or enables the corresponding channels. Read as: \n \n Bit \\[C\\]
74= 0 Channel C is disabled. \n \n Bit \\[C\\]
75= 1 Channel C is enabled. \n \n Write as: \n \n Bit \\[C\\]
76= 0 No effect. Use the chnl_enable_clr Register to disable a channel. \n \n Bit \\[C\\]
77= 1 Enables channel C. \n \n Writing to a bit where a DMA channel is not implemented has no effect."]
78    #[inline(always)]
79    pub fn chnl_enable_set(&self) -> CHNL_ENABLE_SET_R {
80        CHNL_ENABLE_SET_R::new((self.bits & 0xffff) as u16)
81    }
82}
83impl W {
84    #[doc = "Bits 0:15 - Returns the enable status of the channels, or enables the corresponding channels. Read as: \n \n Bit \\[C\\]
85= 0 Channel C is disabled. \n \n Bit \\[C\\]
86= 1 Channel C is enabled. \n \n Write as: \n \n Bit \\[C\\]
87= 0 No effect. Use the chnl_enable_clr Register to disable a channel. \n \n Bit \\[C\\]
88= 1 Enables channel C. \n \n Writing to a bit where a DMA channel is not implemented has no effect."]
89    #[inline(always)]
90    pub fn chnl_enable_set(&mut self) -> CHNL_ENABLE_SET_W {
91        CHNL_ENABLE_SET_W { w: self }
92    }
93    #[doc = "Writes raw bits to the register."]
94    #[inline(always)]
95    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
96        self.0.bits(bits);
97        self
98    }
99}
100#[doc = "Returns the enable status of the channels, or enables the corresponding channels.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_enable_set](index.html) module"]
101pub struct CHNL_ENABLE_SET_SPEC;
102impl crate::RegisterSpec for CHNL_ENABLE_SET_SPEC {
103    type Ux = u32;
104}
105#[doc = "`read()` method returns [chnl_enable_set::R](R) reader structure"]
106impl crate::Readable for CHNL_ENABLE_SET_SPEC {
107    type Reader = R;
108}
109#[doc = "`write(|w| ..)` method takes [chnl_enable_set::W](W) writer structure"]
110impl crate::Writable for CHNL_ENABLE_SET_SPEC {
111    type Writer = W;
112}
113#[doc = "`reset()` method sets CHNL_ENABLE_SET to value 0"]
114impl crate::Resettable for CHNL_ENABLE_SET_SPEC {
115    #[inline(always)]
116    fn reset_value() -> Self::Ux {
117        0
118    }
119}
eos_s3/sdma/chnl_enable_set.rs

eos_s3/sdma/
chnl_enable_set.rs
