1#[doc = "Register `UART_TFR` reader"]
2pub struct R(crate::R<UART_TFR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<UART_TFR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<UART_TFR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<UART_TFR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Field `CTS` reader - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW."]
17pub struct CTS_R(crate::FieldReader<bool, bool>);
18impl CTS_R {
19 #[inline(always)]
20 pub(crate) fn new(bits: bool) -> Self {
21 CTS_R(crate::FieldReader::new(bits))
22 }
23}
24impl core::ops::Deref for CTS_R {
25 type Target = crate::FieldReader<bool, bool>;
26 #[inline(always)]
27 fn deref(&self) -> &Self::Target {
28 &self.0
29 }
30}
31#[doc = "Field `DSR` reader - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW."]
32pub struct DSR_R(crate::FieldReader<bool, bool>);
33impl DSR_R {
34 #[inline(always)]
35 pub(crate) fn new(bits: bool) -> Self {
36 DSR_R(crate::FieldReader::new(bits))
37 }
38}
39impl core::ops::Deref for DSR_R {
40 type Target = crate::FieldReader<bool, bool>;
41 #[inline(always)]
42 fn deref(&self) -> &Self::Target {
43 &self.0
44 }
45}
46#[doc = "Field `DCD` reader - Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW."]
47pub struct DCD_R(crate::FieldReader<bool, bool>);
48impl DCD_R {
49 #[inline(always)]
50 pub(crate) fn new(bits: bool) -> Self {
51 DCD_R(crate::FieldReader::new(bits))
52 }
53}
54impl core::ops::Deref for DCD_R {
55 type Target = crate::FieldReader<bool, bool>;
56 #[inline(always)]
57 fn deref(&self) -> &Self::Target {
58 &self.0
59 }
60}
61#[doc = "Field `BUSY` reader - UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not."]
62pub struct BUSY_R(crate::FieldReader<bool, bool>);
63impl BUSY_R {
64 #[inline(always)]
65 pub(crate) fn new(bits: bool) -> Self {
66 BUSY_R(crate::FieldReader::new(bits))
67 }
68}
69impl core::ops::Deref for BUSY_R {
70 type Target = crate::FieldReader<bool, bool>;
71 #[inline(always)]
72 fn deref(&self) -> &Self::Target {
73 &self.0
74 }
75}
76#[doc = "Field `RXFE` reader - Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty."]
77pub struct RXFE_R(crate::FieldReader<bool, bool>);
78impl RXFE_R {
79 #[inline(always)]
80 pub(crate) fn new(bits: bool) -> Self {
81 RXFE_R(crate::FieldReader::new(bits))
82 }
83}
84impl core::ops::Deref for RXFE_R {
85 type Target = crate::FieldReader<bool, bool>;
86 #[inline(always)]
87 fn deref(&self) -> &Self::Target {
88 &self.0
89 }
90}
91#[doc = "Field `TXFF` reader - Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full."]
92pub struct TXFF_R(crate::FieldReader<bool, bool>);
93impl TXFF_R {
94 #[inline(always)]
95 pub(crate) fn new(bits: bool) -> Self {
96 TXFF_R(crate::FieldReader::new(bits))
97 }
98}
99impl core::ops::Deref for TXFF_R {
100 type Target = crate::FieldReader<bool, bool>;
101 #[inline(always)]
102 fn deref(&self) -> &Self::Target {
103 &self.0
104 }
105}
106#[doc = "Field `RXFF` reader - Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full."]
107pub struct RXFF_R(crate::FieldReader<bool, bool>);
108impl RXFF_R {
109 #[inline(always)]
110 pub(crate) fn new(bits: bool) -> Self {
111 RXFF_R(crate::FieldReader::new(bits))
112 }
113}
114impl core::ops::Deref for RXFF_R {
115 type Target = crate::FieldReader<bool, bool>;
116 #[inline(always)]
117 fn deref(&self) -> &Self::Target {
118 &self.0
119 }
120}
121#[doc = "Field `TXFE` reader - Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H on page 3-12. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register."]
122pub struct TXFE_R(crate::FieldReader<bool, bool>);
123impl TXFE_R {
124 #[inline(always)]
125 pub(crate) fn new(bits: bool) -> Self {
126 TXFE_R(crate::FieldReader::new(bits))
127 }
128}
129impl core::ops::Deref for TXFE_R {
130 type Target = crate::FieldReader<bool, bool>;
131 #[inline(always)]
132 fn deref(&self) -> &Self::Target {
133 &self.0
134 }
135}
136#[doc = "Field `RI` reader - Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW."]
137pub struct RI_R(crate::FieldReader<bool, bool>);
138impl RI_R {
139 #[inline(always)]
140 pub(crate) fn new(bits: bool) -> Self {
141 RI_R(crate::FieldReader::new(bits))
142 }
143}
144impl core::ops::Deref for RI_R {
145 type Target = crate::FieldReader<bool, bool>;
146 #[inline(always)]
147 fn deref(&self) -> &Self::Target {
148 &self.0
149 }
150}
151impl R {
152 #[doc = "Bit 0 - Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW."]
153 #[inline(always)]
154 pub fn cts(&self) -> CTS_R {
155 CTS_R::new((self.bits & 0x01) != 0)
156 }
157 #[doc = "Bit 1 - Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW."]
158 #[inline(always)]
159 pub fn dsr(&self) -> DSR_R {
160 DSR_R::new(((self.bits >> 1) & 0x01) != 0)
161 }
162 #[doc = "Bit 2 - Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW."]
163 #[inline(always)]
164 pub fn dcd(&self) -> DCD_R {
165 DCD_R::new(((self.bits >> 2) & 0x01) != 0)
166 }
167 #[doc = "Bit 3 - UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not."]
168 #[inline(always)]
169 pub fn busy(&self) -> BUSY_R {
170 BUSY_R::new(((self.bits >> 3) & 0x01) != 0)
171 }
172 #[doc = "Bit 4 - Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty."]
173 #[inline(always)]
174 pub fn rxfe(&self) -> RXFE_R {
175 RXFE_R::new(((self.bits >> 4) & 0x01) != 0)
176 }
177 #[doc = "Bit 5 - Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full."]
178 #[inline(always)]
179 pub fn txff(&self) -> TXFF_R {
180 TXFF_R::new(((self.bits >> 5) & 0x01) != 0)
181 }
182 #[doc = "Bit 6 - Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full."]
183 #[inline(always)]
184 pub fn rxff(&self) -> RXFF_R {
185 RXFF_R::new(((self.bits >> 6) & 0x01) != 0)
186 }
187 #[doc = "Bit 7 - Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H on page 3-12. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register."]
188 #[inline(always)]
189 pub fn txfe(&self) -> TXFE_R {
190 TXFE_R::new(((self.bits >> 7) & 0x01) != 0)
191 }
192 #[doc = "Bit 8 - Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW."]
193 #[inline(always)]
194 pub fn ri(&self) -> RI_R {
195 RI_R::new(((self.bits >> 8) & 0x01) != 0)
196 }
197}
198#[doc = "UART Flag Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_tfr](index.html) module"]
199pub struct UART_TFR_SPEC;
200impl crate::RegisterSpec for UART_TFR_SPEC {
201 type Ux = u32;
202}
203#[doc = "`read()` method returns [uart_tfr::R](R) reader structure"]
204impl crate::Readable for UART_TFR_SPEC {
205 type Reader = R;
206}
207#[doc = "`reset()` method sets UART_TFR to value 0"]
208impl crate::Resettable for UART_TFR_SPEC {
209 #[inline(always)]
210 fn reset_value() -> Self::Ux {
211 0
212 }
213}