1#[doc = "Register `UART_IFLS` reader"]
2pub struct R(crate::R<UART_IFLS_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<UART_IFLS_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<UART_IFLS_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<UART_IFLS_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `UART_IFLS` writer"]
17pub struct W(crate::W<UART_IFLS_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<UART_IFLS_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<UART_IFLS_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<UART_IFLS_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Transmit interrupt FIFO level select. The trigger points for the receive interrupt are as follows\n\nValue on reset: 2"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39#[repr(u8)]
40pub enum TXIFLSEL_A {
41 #[doc = "0: Trigger when corresponding FIFO becomes ≤ 1/8 full"]
42 ONE_EIGHT = 0,
43 #[doc = "1: Trigger when corresponding FIFO becomes ≤ 1/4 full"]
44 ONE_QUARTER = 1,
45 #[doc = "2: Trigger when corresponding FIFO becomes ≤ 1/2 full"]
46 ONE_HALF = 2,
47 #[doc = "3: Trigger when corresponding FIFO becomes ≤ 3/4 full"]
48 THREE_QUARTERS = 3,
49 #[doc = "4: Trigger when corresponding FIFO becomes ≤ 7/8 full"]
50 SEVEN_EIGHTS = 4,
51}
52impl From<TXIFLSEL_A> for u8 {
53 #[inline(always)]
54 fn from(variant: TXIFLSEL_A) -> Self {
55 variant as _
56 }
57}
58#[doc = "Field `TXIFLSEL` reader - Transmit interrupt FIFO level select. The trigger points for the receive interrupt are as follows"]
59pub struct TXIFLSEL_R(crate::FieldReader<u8, TXIFLSEL_A>);
60impl TXIFLSEL_R {
61 #[inline(always)]
62 pub(crate) fn new(bits: u8) -> Self {
63 TXIFLSEL_R(crate::FieldReader::new(bits))
64 }
65 #[doc = r"Get enumerated values variant"]
66 #[inline(always)]
67 pub fn variant(&self) -> Option<TXIFLSEL_A> {
68 match self.bits {
69 0 => Some(TXIFLSEL_A::ONE_EIGHT),
70 1 => Some(TXIFLSEL_A::ONE_QUARTER),
71 2 => Some(TXIFLSEL_A::ONE_HALF),
72 3 => Some(TXIFLSEL_A::THREE_QUARTERS),
73 4 => Some(TXIFLSEL_A::SEVEN_EIGHTS),
74 _ => None,
75 }
76 }
77 #[doc = "Checks if the value of the field is `ONE_EIGHT`"]
78 #[inline(always)]
79 pub fn is_one_eight(&self) -> bool {
80 **self == TXIFLSEL_A::ONE_EIGHT
81 }
82 #[doc = "Checks if the value of the field is `ONE_QUARTER`"]
83 #[inline(always)]
84 pub fn is_one_quarter(&self) -> bool {
85 **self == TXIFLSEL_A::ONE_QUARTER
86 }
87 #[doc = "Checks if the value of the field is `ONE_HALF`"]
88 #[inline(always)]
89 pub fn is_one_half(&self) -> bool {
90 **self == TXIFLSEL_A::ONE_HALF
91 }
92 #[doc = "Checks if the value of the field is `THREE_QUARTERS`"]
93 #[inline(always)]
94 pub fn is_three_quarters(&self) -> bool {
95 **self == TXIFLSEL_A::THREE_QUARTERS
96 }
97 #[doc = "Checks if the value of the field is `SEVEN_EIGHTS`"]
98 #[inline(always)]
99 pub fn is_seven_eights(&self) -> bool {
100 **self == TXIFLSEL_A::SEVEN_EIGHTS
101 }
102}
103impl core::ops::Deref for TXIFLSEL_R {
104 type Target = crate::FieldReader<u8, TXIFLSEL_A>;
105 #[inline(always)]
106 fn deref(&self) -> &Self::Target {
107 &self.0
108 }
109}
110#[doc = "Field `TXIFLSEL` writer - Transmit interrupt FIFO level select. The trigger points for the receive interrupt are as follows"]
111pub struct TXIFLSEL_W<'a> {
112 w: &'a mut W,
113}
114impl<'a> TXIFLSEL_W<'a> {
115 #[doc = r"Writes `variant` to the field"]
116 #[inline(always)]
117 pub fn variant(self, variant: TXIFLSEL_A) -> &'a mut W {
118 unsafe { self.bits(variant.into()) }
119 }
120 #[doc = "Trigger when corresponding FIFO becomes ≤ 1/8 full"]
121 #[inline(always)]
122 pub fn one_eight(self) -> &'a mut W {
123 self.variant(TXIFLSEL_A::ONE_EIGHT)
124 }
125 #[doc = "Trigger when corresponding FIFO becomes ≤ 1/4 full"]
126 #[inline(always)]
127 pub fn one_quarter(self) -> &'a mut W {
128 self.variant(TXIFLSEL_A::ONE_QUARTER)
129 }
130 #[doc = "Trigger when corresponding FIFO becomes ≤ 1/2 full"]
131 #[inline(always)]
132 pub fn one_half(self) -> &'a mut W {
133 self.variant(TXIFLSEL_A::ONE_HALF)
134 }
135 #[doc = "Trigger when corresponding FIFO becomes ≤ 3/4 full"]
136 #[inline(always)]
137 pub fn three_quarters(self) -> &'a mut W {
138 self.variant(TXIFLSEL_A::THREE_QUARTERS)
139 }
140 #[doc = "Trigger when corresponding FIFO becomes ≤ 7/8 full"]
141 #[inline(always)]
142 pub fn seven_eights(self) -> &'a mut W {
143 self.variant(TXIFLSEL_A::SEVEN_EIGHTS)
144 }
145 #[doc = r"Writes raw bits to the field"]
146 #[inline(always)]
147 pub unsafe fn bits(self, value: u8) -> &'a mut W {
148 self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
149 self.w
150 }
151}
152#[doc = "Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows"]
153pub type RXIFLSEL_A = TXIFLSEL_A;
154#[doc = "Field `RXIFLSEL` reader - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows"]
155pub type RXIFLSEL_R = TXIFLSEL_R;
156#[doc = "Field `RXIFLSEL` writer - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows"]
157pub struct RXIFLSEL_W<'a> {
158 w: &'a mut W,
159}
160impl<'a> RXIFLSEL_W<'a> {
161 #[doc = r"Writes `variant` to the field"]
162 #[inline(always)]
163 pub fn variant(self, variant: RXIFLSEL_A) -> &'a mut W {
164 unsafe { self.bits(variant.into()) }
165 }
166 #[doc = "Trigger when corresponding FIFO becomes ≤ 1/8 full"]
167 #[inline(always)]
168 pub fn one_eight(self) -> &'a mut W {
169 self.variant(RXIFLSEL_A::ONE_EIGHT)
170 }
171 #[doc = "Trigger when corresponding FIFO becomes ≤ 1/4 full"]
172 #[inline(always)]
173 pub fn one_quarter(self) -> &'a mut W {
174 self.variant(RXIFLSEL_A::ONE_QUARTER)
175 }
176 #[doc = "Trigger when corresponding FIFO becomes ≤ 1/2 full"]
177 #[inline(always)]
178 pub fn one_half(self) -> &'a mut W {
179 self.variant(RXIFLSEL_A::ONE_HALF)
180 }
181 #[doc = "Trigger when corresponding FIFO becomes ≤ 3/4 full"]
182 #[inline(always)]
183 pub fn three_quarters(self) -> &'a mut W {
184 self.variant(RXIFLSEL_A::THREE_QUARTERS)
185 }
186 #[doc = "Trigger when corresponding FIFO becomes ≤ 7/8 full"]
187 #[inline(always)]
188 pub fn seven_eights(self) -> &'a mut W {
189 self.variant(RXIFLSEL_A::SEVEN_EIGHTS)
190 }
191 #[doc = r"Writes raw bits to the field"]
192 #[inline(always)]
193 pub unsafe fn bits(self, value: u8) -> &'a mut W {
194 self.w.bits =
195 (self.w.bits & !(0x07 << 3)) | ((value as u32 & 0x07) << 3);
196 self.w
197 }
198}
199impl R {
200 #[doc = "Bits 0:2 - Transmit interrupt FIFO level select. The trigger points for the receive interrupt are as follows"]
201 #[inline(always)]
202 pub fn txiflsel(&self) -> TXIFLSEL_R {
203 TXIFLSEL_R::new((self.bits & 0x07) as u8)
204 }
205 #[doc = "Bits 3:5 - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows"]
206 #[inline(always)]
207 pub fn rxiflsel(&self) -> RXIFLSEL_R {
208 RXIFLSEL_R::new(((self.bits >> 3) & 0x07) as u8)
209 }
210}
211impl W {
212 #[doc = "Bits 0:2 - Transmit interrupt FIFO level select. The trigger points for the receive interrupt are as follows"]
213 #[inline(always)]
214 pub fn txiflsel(&mut self) -> TXIFLSEL_W {
215 TXIFLSEL_W { w: self }
216 }
217 #[doc = "Bits 3:5 - Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows"]
218 #[inline(always)]
219 pub fn rxiflsel(&mut self) -> RXIFLSEL_W {
220 RXIFLSEL_W { w: self }
221 }
222 #[doc = "Writes raw bits to the register."]
223 #[inline(always)]
224 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
225 self.0.bits(bits);
226 self
227 }
228}
229#[doc = "Interrupt FIFO Level Select Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_ifls](index.html) module"]
230pub struct UART_IFLS_SPEC;
231impl crate::RegisterSpec for UART_IFLS_SPEC {
232 type Ux = u32;
233}
234#[doc = "`read()` method returns [uart_ifls::R](R) reader structure"]
235impl crate::Readable for UART_IFLS_SPEC {
236 type Reader = R;
237}
238#[doc = "`write(|w| ..)` method takes [uart_ifls::W](W) writer structure"]
239impl crate::Writable for UART_IFLS_SPEC {
240 type Writer = W;
241}
242#[doc = "`reset()` method sets UART_IFLS to value 0x12"]
243impl crate::Resettable for UART_IFLS_SPEC {
244 #[inline(always)]
245 fn reset_value() -> Self::Ux {
246 0x12
247 }
248}