1#[doc = "Register `UART_ICR` writer"]
2pub struct W(crate::W<UART_ICR_SPEC>);
3impl core::ops::Deref for W {
4 type Target = crate::W<UART_ICR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl core::ops::DerefMut for W {
11 #[inline(always)]
12 fn deref_mut(&mut self) -> &mut Self::Target {
13 &mut self.0
14 }
15}
16impl From<crate::W<UART_ICR_SPEC>> for W {
17 #[inline(always)]
18 fn from(writer: crate::W<UART_ICR_SPEC>) -> Self {
19 W(writer)
20 }
21}
22#[doc = "Field `RIMIC` writer - nUARTRI modem interrupt clear. Writing a 1 clears the interrupt."]
23pub struct RIMIC_W<'a> {
24 w: &'a mut W,
25}
26impl<'a> RIMIC_W<'a> {
27 #[doc = r"Sets the field bit"]
28 #[inline(always)]
29 pub fn set_bit(self) -> &'a mut W {
30 self.bit(true)
31 }
32 #[doc = r"Clears the field bit"]
33 #[inline(always)]
34 pub fn clear_bit(self) -> &'a mut W {
35 self.bit(false)
36 }
37 #[doc = r"Writes raw bits to the field"]
38 #[inline(always)]
39 pub fn bit(self, value: bool) -> &'a mut W {
40 self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
41 self.w
42 }
43}
44#[doc = "Field `CTSMIC` writer - nUARTCTS modem interrupt clear. Writing a 1 clears the interrupt."]
45pub struct CTSMIC_W<'a> {
46 w: &'a mut W,
47}
48impl<'a> CTSMIC_W<'a> {
49 #[doc = r"Sets the field bit"]
50 #[inline(always)]
51 pub fn set_bit(self) -> &'a mut W {
52 self.bit(true)
53 }
54 #[doc = r"Clears the field bit"]
55 #[inline(always)]
56 pub fn clear_bit(self) -> &'a mut W {
57 self.bit(false)
58 }
59 #[doc = r"Writes raw bits to the field"]
60 #[inline(always)]
61 pub fn bit(self, value: bool) -> &'a mut W {
62 self.w.bits =
63 (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
64 self.w
65 }
66}
67#[doc = "Field `DCDMIC` writer - nUARTDCD modem interrupt clear. Writing a 1 clears the interrupt."]
68pub struct DCDMIC_W<'a> {
69 w: &'a mut W,
70}
71impl<'a> DCDMIC_W<'a> {
72 #[doc = r"Sets the field bit"]
73 #[inline(always)]
74 pub fn set_bit(self) -> &'a mut W {
75 self.bit(true)
76 }
77 #[doc = r"Clears the field bit"]
78 #[inline(always)]
79 pub fn clear_bit(self) -> &'a mut W {
80 self.bit(false)
81 }
82 #[doc = r"Writes raw bits to the field"]
83 #[inline(always)]
84 pub fn bit(self, value: bool) -> &'a mut W {
85 self.w.bits =
86 (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
87 self.w
88 }
89}
90#[doc = "Field `DSRMIC` writer - nUARTDSR modem interrupt clear. Writing a 1 clears the interrupt."]
91pub struct DSRMIC_W<'a> {
92 w: &'a mut W,
93}
94impl<'a> DSRMIC_W<'a> {
95 #[doc = r"Sets the field bit"]
96 #[inline(always)]
97 pub fn set_bit(self) -> &'a mut W {
98 self.bit(true)
99 }
100 #[doc = r"Clears the field bit"]
101 #[inline(always)]
102 pub fn clear_bit(self) -> &'a mut W {
103 self.bit(false)
104 }
105 #[doc = r"Writes raw bits to the field"]
106 #[inline(always)]
107 pub fn bit(self, value: bool) -> &'a mut W {
108 self.w.bits =
109 (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
110 self.w
111 }
112}
113#[doc = "Field `RXIC` writer - Receive interrupt clear. Writing a 1 clears the interrupt."]
114pub struct RXIC_W<'a> {
115 w: &'a mut W,
116}
117impl<'a> RXIC_W<'a> {
118 #[doc = r"Sets the field bit"]
119 #[inline(always)]
120 pub fn set_bit(self) -> &'a mut W {
121 self.bit(true)
122 }
123 #[doc = r"Clears the field bit"]
124 #[inline(always)]
125 pub fn clear_bit(self) -> &'a mut W {
126 self.bit(false)
127 }
128 #[doc = r"Writes raw bits to the field"]
129 #[inline(always)]
130 pub fn bit(self, value: bool) -> &'a mut W {
131 self.w.bits =
132 (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
133 self.w
134 }
135}
136#[doc = "Field `TXIC` writer - Transmit interrupt clear. Writing a 1 clears the interrupt."]
137pub struct TXIC_W<'a> {
138 w: &'a mut W,
139}
140impl<'a> TXIC_W<'a> {
141 #[doc = r"Sets the field bit"]
142 #[inline(always)]
143 pub fn set_bit(self) -> &'a mut W {
144 self.bit(true)
145 }
146 #[doc = r"Clears the field bit"]
147 #[inline(always)]
148 pub fn clear_bit(self) -> &'a mut W {
149 self.bit(false)
150 }
151 #[doc = r"Writes raw bits to the field"]
152 #[inline(always)]
153 pub fn bit(self, value: bool) -> &'a mut W {
154 self.w.bits =
155 (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
156 self.w
157 }
158}
159#[doc = "Field `RTIC` writer - Receive timeout interrupt clear. Writing a 1 clears the interrupt."]
160pub struct RTIC_W<'a> {
161 w: &'a mut W,
162}
163impl<'a> RTIC_W<'a> {
164 #[doc = r"Sets the field bit"]
165 #[inline(always)]
166 pub fn set_bit(self) -> &'a mut W {
167 self.bit(true)
168 }
169 #[doc = r"Clears the field bit"]
170 #[inline(always)]
171 pub fn clear_bit(self) -> &'a mut W {
172 self.bit(false)
173 }
174 #[doc = r"Writes raw bits to the field"]
175 #[inline(always)]
176 pub fn bit(self, value: bool) -> &'a mut W {
177 self.w.bits =
178 (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
179 self.w
180 }
181}
182#[doc = "Field `FEIC` writer - Framing error interrupt clear. Writing a 1 clears the interrupt."]
183pub struct FEIC_W<'a> {
184 w: &'a mut W,
185}
186impl<'a> FEIC_W<'a> {
187 #[doc = r"Sets the field bit"]
188 #[inline(always)]
189 pub fn set_bit(self) -> &'a mut W {
190 self.bit(true)
191 }
192 #[doc = r"Clears the field bit"]
193 #[inline(always)]
194 pub fn clear_bit(self) -> &'a mut W {
195 self.bit(false)
196 }
197 #[doc = r"Writes raw bits to the field"]
198 #[inline(always)]
199 pub fn bit(self, value: bool) -> &'a mut W {
200 self.w.bits =
201 (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
202 self.w
203 }
204}
205#[doc = "Field `PEIC` writer - Parity error interrupt clear. Writing a 1 clears the interrupt."]
206pub struct PEIC_W<'a> {
207 w: &'a mut W,
208}
209impl<'a> PEIC_W<'a> {
210 #[doc = r"Sets the field bit"]
211 #[inline(always)]
212 pub fn set_bit(self) -> &'a mut W {
213 self.bit(true)
214 }
215 #[doc = r"Clears the field bit"]
216 #[inline(always)]
217 pub fn clear_bit(self) -> &'a mut W {
218 self.bit(false)
219 }
220 #[doc = r"Writes raw bits to the field"]
221 #[inline(always)]
222 pub fn bit(self, value: bool) -> &'a mut W {
223 self.w.bits =
224 (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
225 self.w
226 }
227}
228#[doc = "Field `BEIC` writer - Break error interrupt clear. Writing a 1 clears the interrupt."]
229pub struct BEIC_W<'a> {
230 w: &'a mut W,
231}
232impl<'a> BEIC_W<'a> {
233 #[doc = r"Sets the field bit"]
234 #[inline(always)]
235 pub fn set_bit(self) -> &'a mut W {
236 self.bit(true)
237 }
238 #[doc = r"Clears the field bit"]
239 #[inline(always)]
240 pub fn clear_bit(self) -> &'a mut W {
241 self.bit(false)
242 }
243 #[doc = r"Writes raw bits to the field"]
244 #[inline(always)]
245 pub fn bit(self, value: bool) -> &'a mut W {
246 self.w.bits =
247 (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
248 self.w
249 }
250}
251#[doc = "Field `OEIC` writer - Overrun error interrupt clear. Writing a 1 clears the interrupt."]
252pub struct OEIC_W<'a> {
253 w: &'a mut W,
254}
255impl<'a> OEIC_W<'a> {
256 #[doc = r"Sets the field bit"]
257 #[inline(always)]
258 pub fn set_bit(self) -> &'a mut W {
259 self.bit(true)
260 }
261 #[doc = r"Clears the field bit"]
262 #[inline(always)]
263 pub fn clear_bit(self) -> &'a mut W {
264 self.bit(false)
265 }
266 #[doc = r"Writes raw bits to the field"]
267 #[inline(always)]
268 pub fn bit(self, value: bool) -> &'a mut W {
269 self.w.bits =
270 (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
271 self.w
272 }
273}
274impl W {
275 #[doc = "Bit 0 - nUARTRI modem interrupt clear. Writing a 1 clears the interrupt."]
276 #[inline(always)]
277 pub fn rimic(&mut self) -> RIMIC_W {
278 RIMIC_W { w: self }
279 }
280 #[doc = "Bit 1 - nUARTCTS modem interrupt clear. Writing a 1 clears the interrupt."]
281 #[inline(always)]
282 pub fn ctsmic(&mut self) -> CTSMIC_W {
283 CTSMIC_W { w: self }
284 }
285 #[doc = "Bit 2 - nUARTDCD modem interrupt clear. Writing a 1 clears the interrupt."]
286 #[inline(always)]
287 pub fn dcdmic(&mut self) -> DCDMIC_W {
288 DCDMIC_W { w: self }
289 }
290 #[doc = "Bit 3 - nUARTDSR modem interrupt clear. Writing a 1 clears the interrupt."]
291 #[inline(always)]
292 pub fn dsrmic(&mut self) -> DSRMIC_W {
293 DSRMIC_W { w: self }
294 }
295 #[doc = "Bit 4 - Receive interrupt clear. Writing a 1 clears the interrupt."]
296 #[inline(always)]
297 pub fn rxic(&mut self) -> RXIC_W {
298 RXIC_W { w: self }
299 }
300 #[doc = "Bit 5 - Transmit interrupt clear. Writing a 1 clears the interrupt."]
301 #[inline(always)]
302 pub fn txic(&mut self) -> TXIC_W {
303 TXIC_W { w: self }
304 }
305 #[doc = "Bit 6 - Receive timeout interrupt clear. Writing a 1 clears the interrupt."]
306 #[inline(always)]
307 pub fn rtic(&mut self) -> RTIC_W {
308 RTIC_W { w: self }
309 }
310 #[doc = "Bit 7 - Framing error interrupt clear. Writing a 1 clears the interrupt."]
311 #[inline(always)]
312 pub fn feic(&mut self) -> FEIC_W {
313 FEIC_W { w: self }
314 }
315 #[doc = "Bit 8 - Parity error interrupt clear. Writing a 1 clears the interrupt."]
316 #[inline(always)]
317 pub fn peic(&mut self) -> PEIC_W {
318 PEIC_W { w: self }
319 }
320 #[doc = "Bit 9 - Break error interrupt clear. Writing a 1 clears the interrupt."]
321 #[inline(always)]
322 pub fn beic(&mut self) -> BEIC_W {
323 BEIC_W { w: self }
324 }
325 #[doc = "Bit 10 - Overrun error interrupt clear. Writing a 1 clears the interrupt."]
326 #[inline(always)]
327 pub fn oeic(&mut self) -> OEIC_W {
328 OEIC_W { w: self }
329 }
330 #[doc = "Writes raw bits to the register."]
331 #[inline(always)]
332 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
333 self.0.bits(bits);
334 self
335 }
336}
337#[doc = "Interrupt clear register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_icr](index.html) module"]
338pub struct UART_ICR_SPEC;
339impl crate::RegisterSpec for UART_ICR_SPEC {
340 type Ux = u32;
341}
342#[doc = "`write(|w| ..)` method takes [uart_icr::W](W) writer structure"]
343impl crate::Writable for UART_ICR_SPEC {
344 type Writer = W;
345}
346#[doc = "`reset()` method sets UART_ICR to value 0"]
347impl crate::Resettable for UART_ICR_SPEC {
348 #[inline(always)]
349 fn reset_value() -> Self::Ux {
350 0
351 }
352}