1#[doc = "Register `UART_CR` reader"]
2pub struct R(crate::R<UART_CR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<UART_CR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<UART_CR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<UART_CR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `UART_CR` writer"]
17pub struct W(crate::W<UART_CR_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<UART_CR_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<UART_CR_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<UART_CR_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "UART enable\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum UARTEN_A {
40 #[doc = "0: UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping."]
41 UART_DISABLE = 0,
42 #[doc = "1: the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."]
43 UART_ENABLE = 1,
44}
45impl From<UARTEN_A> for bool {
46 #[inline(always)]
47 fn from(variant: UARTEN_A) -> Self {
48 variant as u8 != 0
49 }
50}
51#[doc = "Field `UARTEN` reader - UART enable"]
52pub struct UARTEN_R(crate::FieldReader<bool, UARTEN_A>);
53impl UARTEN_R {
54 #[inline(always)]
55 pub(crate) fn new(bits: bool) -> Self {
56 UARTEN_R(crate::FieldReader::new(bits))
57 }
58 #[doc = r"Get enumerated values variant"]
59 #[inline(always)]
60 pub fn variant(&self) -> UARTEN_A {
61 match self.bits {
62 false => UARTEN_A::UART_DISABLE,
63 true => UARTEN_A::UART_ENABLE,
64 }
65 }
66 #[doc = "Checks if the value of the field is `UART_DISABLE`"]
67 #[inline(always)]
68 pub fn is_uart_disable(&self) -> bool {
69 **self == UARTEN_A::UART_DISABLE
70 }
71 #[doc = "Checks if the value of the field is `UART_ENABLE`"]
72 #[inline(always)]
73 pub fn is_uart_enable(&self) -> bool {
74 **self == UARTEN_A::UART_ENABLE
75 }
76}
77impl core::ops::Deref for UARTEN_R {
78 type Target = crate::FieldReader<bool, UARTEN_A>;
79 #[inline(always)]
80 fn deref(&self) -> &Self::Target {
81 &self.0
82 }
83}
84#[doc = "Field `UARTEN` writer - UART enable"]
85pub struct UARTEN_W<'a> {
86 w: &'a mut W,
87}
88impl<'a> UARTEN_W<'a> {
89 #[doc = r"Writes `variant` to the field"]
90 #[inline(always)]
91 pub fn variant(self, variant: UARTEN_A) -> &'a mut W {
92 self.bit(variant.into())
93 }
94 #[doc = "UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping."]
95 #[inline(always)]
96 pub fn uart_disable(self) -> &'a mut W {
97 self.variant(UARTEN_A::UART_DISABLE)
98 }
99 #[doc = "the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit."]
100 #[inline(always)]
101 pub fn uart_enable(self) -> &'a mut W {
102 self.variant(UARTEN_A::UART_ENABLE)
103 }
104 #[doc = r"Sets the field bit"]
105 #[inline(always)]
106 pub fn set_bit(self) -> &'a mut W {
107 self.bit(true)
108 }
109 #[doc = r"Clears the field bit"]
110 #[inline(always)]
111 pub fn clear_bit(self) -> &'a mut W {
112 self.bit(false)
113 }
114 #[doc = r"Writes raw bits to the field"]
115 #[inline(always)]
116 pub fn bit(self, value: bool) -> &'a mut W {
117 self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
118 self.w
119 }
120}
121#[doc = "Siren enable. This bit has no effect if the UARTEN bit disables the UART.\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq)]
123pub enum SIREN_A {
124 #[doc = "0: IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect."]
125 SIREN_DISABLE = 0,
126 #[doc = "1: IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect."]
127 SIREN_ENABLE = 1,
128}
129impl From<SIREN_A> for bool {
130 #[inline(always)]
131 fn from(variant: SIREN_A) -> Self {
132 variant as u8 != 0
133 }
134}
135#[doc = "Field `SIREN` reader - Siren enable. This bit has no effect if the UARTEN bit disables the UART."]
136pub struct SIREN_R(crate::FieldReader<bool, SIREN_A>);
137impl SIREN_R {
138 #[inline(always)]
139 pub(crate) fn new(bits: bool) -> Self {
140 SIREN_R(crate::FieldReader::new(bits))
141 }
142 #[doc = r"Get enumerated values variant"]
143 #[inline(always)]
144 pub fn variant(&self) -> SIREN_A {
145 match self.bits {
146 false => SIREN_A::SIREN_DISABLE,
147 true => SIREN_A::SIREN_ENABLE,
148 }
149 }
150 #[doc = "Checks if the value of the field is `SIREN_DISABLE`"]
151 #[inline(always)]
152 pub fn is_siren_disable(&self) -> bool {
153 **self == SIREN_A::SIREN_DISABLE
154 }
155 #[doc = "Checks if the value of the field is `SIREN_ENABLE`"]
156 #[inline(always)]
157 pub fn is_siren_enable(&self) -> bool {
158 **self == SIREN_A::SIREN_ENABLE
159 }
160}
161impl core::ops::Deref for SIREN_R {
162 type Target = crate::FieldReader<bool, SIREN_A>;
163 #[inline(always)]
164 fn deref(&self) -> &Self::Target {
165 &self.0
166 }
167}
168#[doc = "Field `SIREN` writer - Siren enable. This bit has no effect if the UARTEN bit disables the UART."]
169pub struct SIREN_W<'a> {
170 w: &'a mut W,
171}
172impl<'a> SIREN_W<'a> {
173 #[doc = r"Writes `variant` to the field"]
174 #[inline(always)]
175 pub fn variant(self, variant: SIREN_A) -> &'a mut W {
176 self.bit(variant.into())
177 }
178 #[doc = "IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect."]
179 #[inline(always)]
180 pub fn siren_disable(self) -> &'a mut W {
181 self.variant(SIREN_A::SIREN_DISABLE)
182 }
183 #[doc = "IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect."]
184 #[inline(always)]
185 pub fn siren_enable(self) -> &'a mut W {
186 self.variant(SIREN_A::SIREN_ENABLE)
187 }
188 #[doc = r"Sets the field bit"]
189 #[inline(always)]
190 pub fn set_bit(self) -> &'a mut W {
191 self.bit(true)
192 }
193 #[doc = r"Clears the field bit"]
194 #[inline(always)]
195 pub fn clear_bit(self) -> &'a mut W {
196 self.bit(false)
197 }
198 #[doc = r"Writes raw bits to the field"]
199 #[inline(always)]
200 pub fn bit(self, value: bool) -> &'a mut W {
201 self.w.bits =
202 (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
203 self.w
204 }
205}
206#[doc = "Field `SIRLP` reader - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."]
207pub struct SIRLP_R(crate::FieldReader<bool, bool>);
208impl SIRLP_R {
209 #[inline(always)]
210 pub(crate) fn new(bits: bool) -> Self {
211 SIRLP_R(crate::FieldReader::new(bits))
212 }
213}
214impl core::ops::Deref for SIRLP_R {
215 type Target = crate::FieldReader<bool, bool>;
216 #[inline(always)]
217 fn deref(&self) -> &Self::Target {
218 &self.0
219 }
220}
221#[doc = "Field `SIRLP` writer - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."]
222pub struct SIRLP_W<'a> {
223 w: &'a mut W,
224}
225impl<'a> SIRLP_W<'a> {
226 #[doc = r"Sets the field bit"]
227 #[inline(always)]
228 pub fn set_bit(self) -> &'a mut W {
229 self.bit(true)
230 }
231 #[doc = r"Clears the field bit"]
232 #[inline(always)]
233 pub fn clear_bit(self) -> &'a mut W {
234 self.bit(false)
235 }
236 #[doc = r"Writes raw bits to the field"]
237 #[inline(always)]
238 pub fn bit(self, value: bool) -> &'a mut W {
239 self.w.bits =
240 (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
241 self.w
242 }
243}
244#[doc = "Field `LBE` reader - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR on page 4-5 is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."]
245pub struct LBE_R(crate::FieldReader<bool, bool>);
246impl LBE_R {
247 #[inline(always)]
248 pub(crate) fn new(bits: bool) -> Self {
249 LBE_R(crate::FieldReader::new(bits))
250 }
251}
252impl core::ops::Deref for LBE_R {
253 type Target = crate::FieldReader<bool, bool>;
254 #[inline(always)]
255 fn deref(&self) -> &Self::Target {
256 &self.0
257 }
258}
259#[doc = "Field `LBE` writer - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR on page 4-5 is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."]
260pub struct LBE_W<'a> {
261 w: &'a mut W,
262}
263impl<'a> LBE_W<'a> {
264 #[doc = r"Sets the field bit"]
265 #[inline(always)]
266 pub fn set_bit(self) -> &'a mut W {
267 self.bit(true)
268 }
269 #[doc = r"Clears the field bit"]
270 #[inline(always)]
271 pub fn clear_bit(self) -> &'a mut W {
272 self.bit(false)
273 }
274 #[doc = r"Writes raw bits to the field"]
275 #[inline(always)]
276 pub fn bit(self, value: bool) -> &'a mut W {
277 self.w.bits =
278 (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
279 self.w
280 }
281}
282#[doc = "Field `TXE` reader - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."]
283pub struct TXE_R(crate::FieldReader<bool, bool>);
284impl TXE_R {
285 #[inline(always)]
286 pub(crate) fn new(bits: bool) -> Self {
287 TXE_R(crate::FieldReader::new(bits))
288 }
289}
290impl core::ops::Deref for TXE_R {
291 type Target = crate::FieldReader<bool, bool>;
292 #[inline(always)]
293 fn deref(&self) -> &Self::Target {
294 &self.0
295 }
296}
297#[doc = "Field `TXE` writer - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."]
298pub struct TXE_W<'a> {
299 w: &'a mut W,
300}
301impl<'a> TXE_W<'a> {
302 #[doc = r"Sets the field bit"]
303 #[inline(always)]
304 pub fn set_bit(self) -> &'a mut W {
305 self.bit(true)
306 }
307 #[doc = r"Clears the field bit"]
308 #[inline(always)]
309 pub fn clear_bit(self) -> &'a mut W {
310 self.bit(false)
311 }
312 #[doc = r"Writes raw bits to the field"]
313 #[inline(always)]
314 pub fn bit(self, value: bool) -> &'a mut W {
315 self.w.bits =
316 (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
317 self.w
318 }
319}
320#[doc = "Field `RXE` reader - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
321pub struct RXE_R(crate::FieldReader<bool, bool>);
322impl RXE_R {
323 #[inline(always)]
324 pub(crate) fn new(bits: bool) -> Self {
325 RXE_R(crate::FieldReader::new(bits))
326 }
327}
328impl core::ops::Deref for RXE_R {
329 type Target = crate::FieldReader<bool, bool>;
330 #[inline(always)]
331 fn deref(&self) -> &Self::Target {
332 &self.0
333 }
334}
335#[doc = "Field `RXE` writer - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
336pub struct RXE_W<'a> {
337 w: &'a mut W,
338}
339impl<'a> RXE_W<'a> {
340 #[doc = r"Sets the field bit"]
341 #[inline(always)]
342 pub fn set_bit(self) -> &'a mut W {
343 self.bit(true)
344 }
345 #[doc = r"Clears the field bit"]
346 #[inline(always)]
347 pub fn clear_bit(self) -> &'a mut W {
348 self.bit(false)
349 }
350 #[doc = r"Writes raw bits to the field"]
351 #[inline(always)]
352 pub fn bit(self, value: bool) -> &'a mut W {
353 self.w.bits =
354 (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
355 self.w
356 }
357}
358#[doc = "Field `DTR` reader - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
359pub struct DTR_R(crate::FieldReader<bool, bool>);
360impl DTR_R {
361 #[inline(always)]
362 pub(crate) fn new(bits: bool) -> Self {
363 DTR_R(crate::FieldReader::new(bits))
364 }
365}
366impl core::ops::Deref for DTR_R {
367 type Target = crate::FieldReader<bool, bool>;
368 #[inline(always)]
369 fn deref(&self) -> &Self::Target {
370 &self.0
371 }
372}
373#[doc = "Field `DTR` writer - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
374pub struct DTR_W<'a> {
375 w: &'a mut W,
376}
377impl<'a> DTR_W<'a> {
378 #[doc = r"Sets the field bit"]
379 #[inline(always)]
380 pub fn set_bit(self) -> &'a mut W {
381 self.bit(true)
382 }
383 #[doc = r"Clears the field bit"]
384 #[inline(always)]
385 pub fn clear_bit(self) -> &'a mut W {
386 self.bit(false)
387 }
388 #[doc = r"Writes raw bits to the field"]
389 #[inline(always)]
390 pub fn bit(self, value: bool) -> &'a mut W {
391 self.w.bits =
392 (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
393 self.w
394 }
395}
396#[doc = "Field `RTS` reader - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."]
397pub struct RTS_R(crate::FieldReader<bool, bool>);
398impl RTS_R {
399 #[inline(always)]
400 pub(crate) fn new(bits: bool) -> Self {
401 RTS_R(crate::FieldReader::new(bits))
402 }
403}
404impl core::ops::Deref for RTS_R {
405 type Target = crate::FieldReader<bool, bool>;
406 #[inline(always)]
407 fn deref(&self) -> &Self::Target {
408 &self.0
409 }
410}
411#[doc = "Field `RTS` writer - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."]
412pub struct RTS_W<'a> {
413 w: &'a mut W,
414}
415impl<'a> RTS_W<'a> {
416 #[doc = r"Sets the field bit"]
417 #[inline(always)]
418 pub fn set_bit(self) -> &'a mut W {
419 self.bit(true)
420 }
421 #[doc = r"Clears the field bit"]
422 #[inline(always)]
423 pub fn clear_bit(self) -> &'a mut W {
424 self.bit(false)
425 }
426 #[doc = r"Writes raw bits to the field"]
427 #[inline(always)]
428 pub fn bit(self, value: bool) -> &'a mut W {
429 self.w.bits =
430 (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
431 self.w
432 }
433}
434#[doc = "Field `Out1` reader - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."]
435pub struct OUT1_R(crate::FieldReader<bool, bool>);
436impl OUT1_R {
437 #[inline(always)]
438 pub(crate) fn new(bits: bool) -> Self {
439 OUT1_R(crate::FieldReader::new(bits))
440 }
441}
442impl core::ops::Deref for OUT1_R {
443 type Target = crate::FieldReader<bool, bool>;
444 #[inline(always)]
445 fn deref(&self) -> &Self::Target {
446 &self.0
447 }
448}
449#[doc = "Field `Out1` writer - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."]
450pub struct OUT1_W<'a> {
451 w: &'a mut W,
452}
453impl<'a> OUT1_W<'a> {
454 #[doc = r"Sets the field bit"]
455 #[inline(always)]
456 pub fn set_bit(self) -> &'a mut W {
457 self.bit(true)
458 }
459 #[doc = r"Clears the field bit"]
460 #[inline(always)]
461 pub fn clear_bit(self) -> &'a mut W {
462 self.bit(false)
463 }
464 #[doc = r"Writes raw bits to the field"]
465 #[inline(always)]
466 pub fn bit(self, value: bool) -> &'a mut W {
467 self.w.bits =
468 (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
469 self.w
470 }
471}
472#[doc = "Field `Out2` reader - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."]
473pub struct OUT2_R(crate::FieldReader<bool, bool>);
474impl OUT2_R {
475 #[inline(always)]
476 pub(crate) fn new(bits: bool) -> Self {
477 OUT2_R(crate::FieldReader::new(bits))
478 }
479}
480impl core::ops::Deref for OUT2_R {
481 type Target = crate::FieldReader<bool, bool>;
482 #[inline(always)]
483 fn deref(&self) -> &Self::Target {
484 &self.0
485 }
486}
487#[doc = "Field `Out2` writer - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."]
488pub struct OUT2_W<'a> {
489 w: &'a mut W,
490}
491impl<'a> OUT2_W<'a> {
492 #[doc = r"Sets the field bit"]
493 #[inline(always)]
494 pub fn set_bit(self) -> &'a mut W {
495 self.bit(true)
496 }
497 #[doc = r"Clears the field bit"]
498 #[inline(always)]
499 pub fn clear_bit(self) -> &'a mut W {
500 self.bit(false)
501 }
502 #[doc = r"Writes raw bits to the field"]
503 #[inline(always)]
504 pub fn bit(self, value: bool) -> &'a mut W {
505 self.w.bits =
506 (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
507 self.w
508 }
509}
510#[doc = "Field `RTSEn` reader - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."]
511pub struct RTSEN_R(crate::FieldReader<bool, bool>);
512impl RTSEN_R {
513 #[inline(always)]
514 pub(crate) fn new(bits: bool) -> Self {
515 RTSEN_R(crate::FieldReader::new(bits))
516 }
517}
518impl core::ops::Deref for RTSEN_R {
519 type Target = crate::FieldReader<bool, bool>;
520 #[inline(always)]
521 fn deref(&self) -> &Self::Target {
522 &self.0
523 }
524}
525#[doc = "Field `RTSEn` writer - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."]
526pub struct RTSEN_W<'a> {
527 w: &'a mut W,
528}
529impl<'a> RTSEN_W<'a> {
530 #[doc = r"Sets the field bit"]
531 #[inline(always)]
532 pub fn set_bit(self) -> &'a mut W {
533 self.bit(true)
534 }
535 #[doc = r"Clears the field bit"]
536 #[inline(always)]
537 pub fn clear_bit(self) -> &'a mut W {
538 self.bit(false)
539 }
540 #[doc = r"Writes raw bits to the field"]
541 #[inline(always)]
542 pub fn bit(self, value: bool) -> &'a mut W {
543 self.w.bits =
544 (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
545 self.w
546 }
547}
548#[doc = "Field `CTSEn` reader - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."]
549pub struct CTSEN_R(crate::FieldReader<bool, bool>);
550impl CTSEN_R {
551 #[inline(always)]
552 pub(crate) fn new(bits: bool) -> Self {
553 CTSEN_R(crate::FieldReader::new(bits))
554 }
555}
556impl core::ops::Deref for CTSEN_R {
557 type Target = crate::FieldReader<bool, bool>;
558 #[inline(always)]
559 fn deref(&self) -> &Self::Target {
560 &self.0
561 }
562}
563#[doc = "Field `CTSEn` writer - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."]
564pub struct CTSEN_W<'a> {
565 w: &'a mut W,
566}
567impl<'a> CTSEN_W<'a> {
568 #[doc = r"Sets the field bit"]
569 #[inline(always)]
570 pub fn set_bit(self) -> &'a mut W {
571 self.bit(true)
572 }
573 #[doc = r"Clears the field bit"]
574 #[inline(always)]
575 pub fn clear_bit(self) -> &'a mut W {
576 self.bit(false)
577 }
578 #[doc = r"Writes raw bits to the field"]
579 #[inline(always)]
580 pub fn bit(self, value: bool) -> &'a mut W {
581 self.w.bits =
582 (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
583 self.w
584 }
585}
586impl R {
587 #[doc = "Bit 0 - UART enable"]
588 #[inline(always)]
589 pub fn uarten(&self) -> UARTEN_R {
590 UARTEN_R::new((self.bits & 0x01) != 0)
591 }
592 #[doc = "Bit 1 - Siren enable. This bit has no effect if the UARTEN bit disables the UART."]
593 #[inline(always)]
594 pub fn siren(&self) -> SIREN_R {
595 SIREN_R::new(((self.bits >> 1) & 0x01) != 0)
596 }
597 #[doc = "Bit 2 - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."]
598 #[inline(always)]
599 pub fn sirlp(&self) -> SIRLP_R {
600 SIRLP_R::new(((self.bits >> 2) & 0x01) != 0)
601 }
602 #[doc = "Bit 7 - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR on page 4-5 is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."]
603 #[inline(always)]
604 pub fn lbe(&self) -> LBE_R {
605 LBE_R::new(((self.bits >> 7) & 0x01) != 0)
606 }
607 #[doc = "Bit 8 - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."]
608 #[inline(always)]
609 pub fn txe(&self) -> TXE_R {
610 TXE_R::new(((self.bits >> 8) & 0x01) != 0)
611 }
612 #[doc = "Bit 9 - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
613 #[inline(always)]
614 pub fn rxe(&self) -> RXE_R {
615 RXE_R::new(((self.bits >> 9) & 0x01) != 0)
616 }
617 #[doc = "Bit 10 - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
618 #[inline(always)]
619 pub fn dtr(&self) -> DTR_R {
620 DTR_R::new(((self.bits >> 10) & 0x01) != 0)
621 }
622 #[doc = "Bit 11 - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."]
623 #[inline(always)]
624 pub fn rts(&self) -> RTS_R {
625 RTS_R::new(((self.bits >> 11) & 0x01) != 0)
626 }
627 #[doc = "Bit 12 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."]
628 #[inline(always)]
629 pub fn out1(&self) -> OUT1_R {
630 OUT1_R::new(((self.bits >> 12) & 0x01) != 0)
631 }
632 #[doc = "Bit 13 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."]
633 #[inline(always)]
634 pub fn out2(&self) -> OUT2_R {
635 OUT2_R::new(((self.bits >> 13) & 0x01) != 0)
636 }
637 #[doc = "Bit 14 - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."]
638 #[inline(always)]
639 pub fn rtsen(&self) -> RTSEN_R {
640 RTSEN_R::new(((self.bits >> 14) & 0x01) != 0)
641 }
642 #[doc = "Bit 15 - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."]
643 #[inline(always)]
644 pub fn ctsen(&self) -> CTSEN_R {
645 CTSEN_R::new(((self.bits >> 15) & 0x01) != 0)
646 }
647}
648impl W {
649 #[doc = "Bit 0 - UART enable"]
650 #[inline(always)]
651 pub fn uarten(&mut self) -> UARTEN_W {
652 UARTEN_W { w: self }
653 }
654 #[doc = "Bit 1 - Siren enable. This bit has no effect if the UARTEN bit disables the UART."]
655 #[inline(always)]
656 pub fn siren(&mut self) -> SIREN_W {
657 SIREN_W { w: self }
658 }
659 #[doc = "Bit 2 - SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances."]
660 #[inline(always)]
661 pub fn sirlp(&mut self) -> SIRLP_W {
662 SIRLP_W { w: self }
663 }
664 #[doc = "Bit 7 - Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR on page 4-5 is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback."]
665 #[inline(always)]
666 pub fn lbe(&mut self) -> LBE_W {
667 LBE_W { w: self }
668 }
669 #[doc = "Bit 8 - Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping."]
670 #[inline(always)]
671 pub fn txe(&mut self) -> TXE_W {
672 TXE_W { w: self }
673 }
674 #[doc = "Bit 9 - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
675 #[inline(always)]
676 pub fn rxe(&mut self) -> RXE_W {
677 RXE_W { w: self }
678 }
679 #[doc = "Bit 10 - Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping."]
680 #[inline(always)]
681 pub fn dtr(&mut self) -> DTR_W {
682 DTR_W { w: self }
683 }
684 #[doc = "Bit 11 - Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW."]
685 #[inline(always)]
686 pub fn rts(&mut self) -> RTS_W {
687 RTS_W { w: self }
688 }
689 #[doc = "Bit 12 - This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD)."]
690 #[inline(always)]
691 pub fn out1(&mut self) -> OUT1_W {
692 OUT1_W { w: self }
693 }
694 #[doc = "Bit 13 - This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI)."]
695 #[inline(always)]
696 pub fn out2(&mut self) -> OUT2_W {
697 OUT2_W { w: self }
698 }
699 #[doc = "Bit 14 - RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received."]
700 #[inline(always)]
701 pub fn rtsen(&mut self) -> RTSEN_W {
702 RTSEN_W { w: self }
703 }
704 #[doc = "Bit 15 - CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted."]
705 #[inline(always)]
706 pub fn ctsen(&mut self) -> CTSEN_W {
707 CTSEN_W { w: self }
708 }
709 #[doc = "Writes raw bits to the register."]
710 #[inline(always)]
711 pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
712 self.0.bits(bits);
713 self
714 }
715}
716#[doc = "UART Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [uart_cr](index.html) module"]
717pub struct UART_CR_SPEC;
718impl crate::RegisterSpec for UART_CR_SPEC {
719 type Ux = u32;
720}
721#[doc = "`read()` method returns [uart_cr::R](R) reader structure"]
722impl crate::Readable for UART_CR_SPEC {
723 type Reader = R;
724}
725#[doc = "`write(|w| ..)` method takes [uart_cr::W](W) writer structure"]
726impl crate::Writable for UART_CR_SPEC {
727 type Writer = W;
728}
729#[doc = "`reset()` method sets UART_CR to value 0"]
730impl crate::Resettable for UART_CR_SPEC {
731 #[inline(always)]
732 fn reset_value() -> Self::Ux {
733 0
734 }
735}