1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4 _reserved_0_uart: [u8; 0x04],
5 #[doc = "0x04 - UART receive status register/error clear register. (WC)"]
6 pub uart_rsr: crate::Reg<uart_rsr::UART_RSR_SPEC>,
7 _reserved2: [u8; 0x10],
8 #[doc = "0x18 - UART Flag Register"]
9 pub uart_tfr: crate::Reg<uart_tfr::UART_TFR_SPEC>,
10 _reserved3: [u8; 0x04],
11 #[doc = "0x20 - 8-bit low-power divisor value."]
12 pub uart_ilpr: crate::Reg<uart_ilpr::UART_ILPR_SPEC>,
13 _reserved4: [u8; 0x08],
14 #[doc = "0x2c - UART Line Control Register. This register accesses bit 29 to 22 of the UART Line Control Register, UARTLCR."]
15 pub uart_lcr_h: crate::Reg<uart_lcr_h::UART_LCR_H_SPEC>,
16 #[doc = "0x30 - UART Control Register"]
17 pub uart_cr: crate::Reg<uart_cr::UART_CR_SPEC>,
18 #[doc = "0x34 - Interrupt FIFO Level Select Register"]
19 pub uart_ifls: crate::Reg<uart_ifls::UART_IFLS_SPEC>,
20 #[doc = "0x38 - Interrupt Mask Set/Clear Register"]
21 pub uart_imsc: crate::Reg<uart_imsc::UART_IMSC_SPEC>,
22 #[doc = "0x3c - Raw interrupt status register"]
23 pub uart_ris: crate::Reg<uart_ris::UART_RIS_SPEC>,
24 #[doc = "0x40 - Masked interrupt status register"]
25 pub uart_mis: crate::Reg<uart_mis::UART_MIS_SPEC>,
26 #[doc = "0x44 - Interrupt clear register"]
27 pub uart_icr: crate::Reg<uart_icr::UART_ICR_SPEC>,
28 _reserved11: [u8; 0x38],
29 #[doc = "0x80 - Test Control Register"]
30 pub uart_tcr: crate::Reg<uart_tcr::UART_TCR_SPEC>,
31 #[doc = "0x84 - Integration test input register"]
32 pub uart_itip: crate::Reg<uart_itip::UART_ITIP_SPEC>,
33 #[doc = "0x88 - Integration test output register"]
34 pub uart_itop: crate::Reg<uart_itop::UART_ITOP_SPEC>,
35 #[doc = "0x8c - Test data register"]
36 pub uart_tdr: crate::Reg<uart_tdr::UART_TDR_SPEC>,
37 _reserved15: [u8; 0x0f50],
38 #[doc = "0xfe0 - UART Peripheral ID 0 register"]
39 pub uart_periph_id0: crate::Reg<uart_periph_id0::UART_PERIPHID0_SPEC>,
40 #[doc = "0xfe4 - UART Peripheral ID 1 register"]
41 pub uart_periph_id1: crate::Reg<uart_periph_id1::UART_PERIPHID1_SPEC>,
42 #[doc = "0xfe8 - UART Peripheral ID 2 register"]
43 pub uart_periph_id2: crate::Reg<uart_periph_id2::UART_PERIPHID2_SPEC>,
44 #[doc = "0xfec - UART Peripheral ID 3 register"]
45 pub uart_periph_id3: crate::Reg<uart_periph_id3::UART_PERIPHID3_SPEC>,
46 #[doc = "0xff0 - UART PCell ID 0 register"]
47 pub uart_pcell_id0: crate::Reg<uart_pcell_id0::UART_PCELLID0_SPEC>,
48 #[doc = "0xff4 - UART PCell ID 1 register"]
49 pub uart_pcell_id1: crate::Reg<uart_pcell_id1::UART_PCELLID1_SPEC>,
50 #[doc = "0xff8 - UART PCell ID 2 register"]
51 pub uart_pcell_id2: crate::Reg<uart_pcell_id2::UART_PCELLID2_SPEC>,
52 #[doc = "0xffc - UART PCell ID 4 register"]
53 pub uart_pcell_id4: crate::Reg<uart_pcell_id4::UART_PCELLID4_SPEC>,
54}
55impl RegisterBlock {
56 #[doc = "0x00 - The fractional baud rate divisor."]
57 #[inline(always)]
58 pub fn uart_fbrd(&self) -> &crate::Reg<uart_fbrd::UART_FBRD_SPEC> {
59 unsafe {
60 &*(((self as *const Self) as *const u8).add(0usize)
61 as *const crate::Reg<uart_fbrd::UART_FBRD_SPEC>)
62 }
63 }
64 #[doc = "0x00 - The integer baud rate divisor."]
65 #[inline(always)]
66 pub fn uart_ibrd(&self) -> &crate::Reg<uart_ibrd::UART_IBRD_SPEC> {
67 unsafe {
68 &*(((self as *const Self) as *const u8).add(0usize)
69 as *const crate::Reg<uart_ibrd::UART_IBRD_SPEC>)
70 }
71 }
72 #[doc = "0x00 - Uart Data register"]
73 #[inline(always)]
74 pub fn uart_dr(&self) -> &crate::Reg<uart_dr::UART_DR_SPEC> {
75 unsafe {
76 &*(((self as *const Self) as *const u8).add(0usize)
77 as *const crate::Reg<uart_dr::UART_DR_SPEC>)
78 }
79 }
80}
81#[doc = "UART_DR register accessor: an alias for `Reg<UART_DR_SPEC>`"]
82pub type UART_DR = crate::Reg<uart_dr::UART_DR_SPEC>;
83#[doc = "Uart Data register"]
84pub mod uart_dr;
85#[doc = "UART_RSR register accessor: an alias for `Reg<UART_RSR_SPEC>`"]
86pub type UART_RSR = crate::Reg<uart_rsr::UART_RSR_SPEC>;
87#[doc = "UART receive status register/error clear register. (WC)"]
88pub mod uart_rsr;
89#[doc = "UART_TFR register accessor: an alias for `Reg<UART_TFR_SPEC>`"]
90pub type UART_TFR = crate::Reg<uart_tfr::UART_TFR_SPEC>;
91#[doc = "UART Flag Register"]
92pub mod uart_tfr;
93#[doc = "UART_ILPR register accessor: an alias for `Reg<UART_ILPR_SPEC>`"]
94pub type UART_ILPR = crate::Reg<uart_ilpr::UART_ILPR_SPEC>;
95#[doc = "8-bit low-power divisor value."]
96pub mod uart_ilpr;
97#[doc = "UART_IBRD register accessor: an alias for `Reg<UART_IBRD_SPEC>`"]
98pub type UART_IBRD = crate::Reg<uart_ibrd::UART_IBRD_SPEC>;
99#[doc = "The integer baud rate divisor."]
100pub mod uart_ibrd;
101#[doc = "UART_FBRD register accessor: an alias for `Reg<UART_FBRD_SPEC>`"]
102pub type UART_FBRD = crate::Reg<uart_fbrd::UART_FBRD_SPEC>;
103#[doc = "The fractional baud rate divisor."]
104pub mod uart_fbrd;
105#[doc = "UART_LCR_H register accessor: an alias for `Reg<UART_LCR_H_SPEC>`"]
106pub type UART_LCR_H = crate::Reg<uart_lcr_h::UART_LCR_H_SPEC>;
107#[doc = "UART Line Control Register. This register accesses bit 29 to 22 of the UART Line Control Register, UARTLCR."]
108pub mod uart_lcr_h;
109#[doc = "UART_CR register accessor: an alias for `Reg<UART_CR_SPEC>`"]
110pub type UART_CR = crate::Reg<uart_cr::UART_CR_SPEC>;
111#[doc = "UART Control Register"]
112pub mod uart_cr;
113#[doc = "UART_IFLS register accessor: an alias for `Reg<UART_IFLS_SPEC>`"]
114pub type UART_IFLS = crate::Reg<uart_ifls::UART_IFLS_SPEC>;
115#[doc = "Interrupt FIFO Level Select Register"]
116pub mod uart_ifls;
117#[doc = "UART_IMSC register accessor: an alias for `Reg<UART_IMSC_SPEC>`"]
118pub type UART_IMSC = crate::Reg<uart_imsc::UART_IMSC_SPEC>;
119#[doc = "Interrupt Mask Set/Clear Register"]
120pub mod uart_imsc;
121#[doc = "UART_RIS register accessor: an alias for `Reg<UART_RIS_SPEC>`"]
122pub type UART_RIS = crate::Reg<uart_ris::UART_RIS_SPEC>;
123#[doc = "Raw interrupt status register"]
124pub mod uart_ris;
125#[doc = "UART_MIS register accessor: an alias for `Reg<UART_MIS_SPEC>`"]
126pub type UART_MIS = crate::Reg<uart_mis::UART_MIS_SPEC>;
127#[doc = "Masked interrupt status register"]
128pub mod uart_mis;
129#[doc = "UART_ICR register accessor: an alias for `Reg<UART_ICR_SPEC>`"]
130pub type UART_ICR = crate::Reg<uart_icr::UART_ICR_SPEC>;
131#[doc = "Interrupt clear register"]
132pub mod uart_icr;
133#[doc = "UART_TCR register accessor: an alias for `Reg<UART_TCR_SPEC>`"]
134pub type UART_TCR = crate::Reg<uart_tcr::UART_TCR_SPEC>;
135#[doc = "Test Control Register"]
136pub mod uart_tcr;
137#[doc = "UART_ITIP register accessor: an alias for `Reg<UART_ITIP_SPEC>`"]
138pub type UART_ITIP = crate::Reg<uart_itip::UART_ITIP_SPEC>;
139#[doc = "Integration test input register"]
140pub mod uart_itip;
141#[doc = "UART_ITOP register accessor: an alias for `Reg<UART_ITOP_SPEC>`"]
142pub type UART_ITOP = crate::Reg<uart_itop::UART_ITOP_SPEC>;
143#[doc = "Integration test output register"]
144pub mod uart_itop;
145#[doc = "UART_TDR register accessor: an alias for `Reg<UART_TDR_SPEC>`"]
146pub type UART_TDR = crate::Reg<uart_tdr::UART_TDR_SPEC>;
147#[doc = "Test data register"]
148pub mod uart_tdr;
149#[doc = "UART_PeriphID0 register accessor: an alias for `Reg<UART_PERIPHID0_SPEC>`"]
150pub type UART_PERIPHID0 = crate::Reg<uart_periph_id0::UART_PERIPHID0_SPEC>;
151#[doc = "UART Peripheral ID 0 register"]
152pub mod uart_periph_id0;
153#[doc = "UART_PeriphID1 register accessor: an alias for `Reg<UART_PERIPHID1_SPEC>`"]
154pub type UART_PERIPHID1 = crate::Reg<uart_periph_id1::UART_PERIPHID1_SPEC>;
155#[doc = "UART Peripheral ID 1 register"]
156pub mod uart_periph_id1;
157#[doc = "UART_PeriphID2 register accessor: an alias for `Reg<UART_PERIPHID2_SPEC>`"]
158pub type UART_PERIPHID2 = crate::Reg<uart_periph_id2::UART_PERIPHID2_SPEC>;
159#[doc = "UART Peripheral ID 2 register"]
160pub mod uart_periph_id2;
161#[doc = "UART_PeriphID3 register accessor: an alias for `Reg<UART_PERIPHID3_SPEC>`"]
162pub type UART_PERIPHID3 = crate::Reg<uart_periph_id3::UART_PERIPHID3_SPEC>;
163#[doc = "UART Peripheral ID 3 register"]
164pub mod uart_periph_id3;
165#[doc = "UART_PCellID0 register accessor: an alias for `Reg<UART_PCELLID0_SPEC>`"]
166pub type UART_PCELLID0 = crate::Reg<uart_pcell_id0::UART_PCELLID0_SPEC>;
167#[doc = "UART PCell ID 0 register"]
168pub mod uart_pcell_id0;
169#[doc = "UART_PCellID1 register accessor: an alias for `Reg<UART_PCELLID1_SPEC>`"]
170pub type UART_PCELLID1 = crate::Reg<uart_pcell_id1::UART_PCELLID1_SPEC>;
171#[doc = "UART PCell ID 1 register"]
172pub mod uart_pcell_id1;
173#[doc = "UART_PCellID2 register accessor: an alias for `Reg<UART_PCELLID2_SPEC>`"]
174pub type UART_PCELLID2 = crate::Reg<uart_pcell_id2::UART_PCELLID2_SPEC>;
175#[doc = "UART PCell ID 2 register"]
176pub mod uart_pcell_id2;
177#[doc = "UART_PCellID4 register accessor: an alias for `Reg<UART_PCELLID4_SPEC>`"]
178pub type UART_PCELLID4 = crate::Reg<uart_pcell_id4::UART_PCELLID4_SPEC>;
179#[doc = "UART PCell ID 4 register"]
180pub mod uart_pcell_id4;