eos_s3/spi_tlc/
mem_addr_byte0.rs

1#[doc = "Register `MemAddrByte0` reader"]
2pub struct R(crate::R<MEMADDRBYTE0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MEMADDRBYTE0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MEMADDRBYTE0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MEMADDRBYTE0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MemAddrByte0` writer"]
17pub struct W(crate::W<MEMADDRBYTE0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MEMADDRBYTE0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MEMADDRBYTE0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MEMADDRBYTE0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MemAddrByte0` reader - Memory Address, It is representing AHB Byte Address bit \\[7:0\\]. \n Bit 7:0 R/W, Default All 0 \n Bit \\[1:0\\]
38will be ignored since only Support Word Access"]
39pub struct MEMADDRBYTE0_R(crate::FieldReader<u8, u8>);
40impl MEMADDRBYTE0_R {
41    #[inline(always)]
42    pub(crate) fn new(bits: u8) -> Self {
43        MEMADDRBYTE0_R(crate::FieldReader::new(bits))
44    }
45}
46impl core::ops::Deref for MEMADDRBYTE0_R {
47    type Target = crate::FieldReader<u8, u8>;
48    #[inline(always)]
49    fn deref(&self) -> &Self::Target {
50        &self.0
51    }
52}
53#[doc = "Field `MemAddrByte0` writer - Memory Address, It is representing AHB Byte Address bit \\[7:0\\]. \n Bit 7:0 R/W, Default All 0 \n Bit \\[1:0\\]
54will be ignored since only Support Word Access"]
55pub struct MEMADDRBYTE0_W<'a> {
56    w: &'a mut W,
57}
58impl<'a> MEMADDRBYTE0_W<'a> {
59    #[doc = r"Writes raw bits to the field"]
60    #[inline(always)]
61    pub unsafe fn bits(self, value: u8) -> &'a mut W {
62        self.w.bits = value as u8;
63        self.w
64    }
65}
66impl R {
67    #[doc = "Bits 0:7 - Memory Address, It is representing AHB Byte Address bit \\[7:0\\]. \n Bit 7:0 R/W, Default All 0 \n Bit \\[1:0\\]
68will be ignored since only Support Word Access"]
69    #[inline(always)]
70    pub fn mem_addr_byte0(&self) -> MEMADDRBYTE0_R {
71        MEMADDRBYTE0_R::new(self.bits as u8)
72    }
73}
74impl W {
75    #[doc = "Bits 0:7 - Memory Address, It is representing AHB Byte Address bit \\[7:0\\]. \n Bit 7:0 R/W, Default All 0 \n Bit \\[1:0\\]
76will be ignored since only Support Word Access"]
77    #[inline(always)]
78    pub fn mem_addr_byte0(&mut self) -> MEMADDRBYTE0_W {
79        MEMADDRBYTE0_W { w: self }
80    }
81    #[doc = "Writes raw bits to the register."]
82    #[inline(always)]
83    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
84        self.0.bits(bits);
85        self
86    }
87}
88#[doc = "Memory Address, It is representing AHB Byte Address bit \\[7:0\\]. \n Bit 7:0 R/W, Default All 0 \n Bit \\[1:0\\]
89will be ignored since only Support Word Access\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mem_addr_byte0](index.html) module"]
90pub struct MEMADDRBYTE0_SPEC;
91impl crate::RegisterSpec for MEMADDRBYTE0_SPEC {
92    type Ux = u8;
93}
94#[doc = "`read()` method returns [mem_addr_byte0::R](R) reader structure"]
95impl crate::Readable for MEMADDRBYTE0_SPEC {
96    type Reader = R;
97}
98#[doc = "`write(|w| ..)` method takes [mem_addr_byte0::W](W) writer structure"]
99impl crate::Writable for MEMADDRBYTE0_SPEC {
100    type Writer = W;
101}
102#[doc = "`reset()` method sets MemAddrByte0 to value 0"]
103impl crate::Resettable for MEMADDRBYTE0_SPEC {
104    #[inline(always)]
105    fn reset_value() -> Self::Ux {
106        0
107    }
108}
eos_s3/spi_tlc/mem_addr_byte0.rs

eos_s3/spi_tlc/
mem_addr_byte0.rs
