eos_s3/spi_tlc/
cm_fifo_0_data.rs

1#[doc = "Register `CM_FIFO_0_DATA` reader"]
2pub struct R(crate::R<CM_FIFO_0_DATA_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CM_FIFO_0_DATA_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CM_FIFO_0_DATA_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CM_FIFO_0_DATA_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `DATA` reader - PF FIFO Read Port"]
17pub struct DATA_R(crate::FieldReader<u8, u8>);
18impl DATA_R {
19    #[inline(always)]
20    pub(crate) fn new(bits: u8) -> Self {
21        DATA_R(crate::FieldReader::new(bits))
22    }
23}
24impl core::ops::Deref for DATA_R {
25    type Target = crate::FieldReader<u8, u8>;
26    #[inline(always)]
27    fn deref(&self) -> &Self::Target {
28        &self.0
29    }
30}
31impl R {
32    #[doc = "Bits 0:7 - PF FIFO Read Port"]
33    #[inline(always)]
34    pub fn data(&self) -> DATA_R {
35        DATA_R::new(self.bits as u8)
36    }
37}
38#[doc = "PF Bank FIFO 0 Read Port\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [cm_fifo_0_data](index.html) module"]
39pub struct CM_FIFO_0_DATA_SPEC;
40impl crate::RegisterSpec for CM_FIFO_0_DATA_SPEC {
41    type Ux = u8;
42}
43#[doc = "`read()` method returns [cm_fifo_0_data::R](R) reader structure"]
44impl crate::Readable for CM_FIFO_0_DATA_SPEC {
45    type Reader = R;
46}
47#[doc = "`reset()` method sets CM_FIFO_0_DATA to value 0"]
48impl crate::Resettable for CM_FIFO_0_DATA_SPEC {
49    #[inline(always)]
50    fn reset_value() -> Self::Ux {
51        0
52    }
53}
eos_s3/spi_tlc/cm_fifo_0_data.rs

eos_s3/spi_tlc/
cm_fifo_0_data.rs
