eos_s3/spi_tlc/
ahbaccessctl.rs

1#[doc = "Register `AHBACCESSCTL` reader"]
2pub struct R(crate::R<AHBACCESSCTL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<AHBACCESSCTL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<AHBACCESSCTL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<AHBACCESSCTL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `AHBACCESSCTL` writer"]
17pub struct W(crate::W<AHBACCESSCTL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<AHBACCESSCTL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<AHBACCESSCTL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<AHBACCESSCTL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `AhbReadReqMode` reader - AHB Memory Read Option \n 2'b11 : If MemAddrByte\\[1:0\\]
38is 2'b11, then AHB Memory Read will not be automatically triggered once MemAddrByte1 is written Other : The AHB Memory Read behavior is same as S2, Once MemAddrByte1 is written, AHB Memory read is triggered."]
39pub struct AHBREADREQMODE_R(crate::FieldReader<u8, u8>);
40impl AHBREADREQMODE_R {
41    #[inline(always)]
42    pub(crate) fn new(bits: u8) -> Self {
43        AHBREADREQMODE_R(crate::FieldReader::new(bits))
44    }
45}
46impl core::ops::Deref for AHBREADREQMODE_R {
47    type Target = crate::FieldReader<u8, u8>;
48    #[inline(always)]
49    fn deref(&self) -> &Self::Target {
50        &self.0
51    }
52}
53#[doc = "Field `AhbReadReqMode` writer - AHB Memory Read Option \n 2'b11 : If MemAddrByte\\[1:0\\]
54is 2'b11, then AHB Memory Read will not be automatically triggered once MemAddrByte1 is written Other : The AHB Memory Read behavior is same as S2, Once MemAddrByte1 is written, AHB Memory read is triggered."]
55pub struct AHBREADREQMODE_W<'a> {
56    w: &'a mut W,
57}
58impl<'a> AHBREADREQMODE_W<'a> {
59    #[doc = r"Writes raw bits to the field"]
60    #[inline(always)]
61    pub unsafe fn bits(self, value: u8) -> &'a mut W {
62        self.w.bits = (self.w.bits & !0x03) | (value as u8 & 0x03);
63        self.w
64    }
65}
66#[doc = "Field `scratch0` reader - General Purpose Registers"]
67pub struct SCRATCH0_R(crate::FieldReader<u8, u8>);
68impl SCRATCH0_R {
69    #[inline(always)]
70    pub(crate) fn new(bits: u8) -> Self {
71        SCRATCH0_R(crate::FieldReader::new(bits))
72    }
73}
74impl core::ops::Deref for SCRATCH0_R {
75    type Target = crate::FieldReader<u8, u8>;
76    #[inline(always)]
77    fn deref(&self) -> &Self::Target {
78        &self.0
79    }
80}
81#[doc = "Field `scratch0` writer - General Purpose Registers"]
82pub struct SCRATCH0_W<'a> {
83    w: &'a mut W,
84}
85impl<'a> SCRATCH0_W<'a> {
86    #[doc = r"Writes raw bits to the field"]
87    #[inline(always)]
88    pub unsafe fn bits(self, value: u8) -> &'a mut W {
89        self.w.bits =
90            (self.w.bits & !(0x3f << 2)) | ((value as u8 & 0x3f) << 2);
91        self.w
92    }
93}
94impl R {
95    #[doc = "Bits 0:1 - AHB Memory Read Option \n 2'b11 : If MemAddrByte\\[1:0\\]
96is 2'b11, then AHB Memory Read will not be automatically triggered once MemAddrByte1 is written Other : The AHB Memory Read behavior is same as S2, Once MemAddrByte1 is written, AHB Memory read is triggered."]
97    #[inline(always)]
98    pub fn ahb_read_req_mode(&self) -> AHBREADREQMODE_R {
99        AHBREADREQMODE_R::new((self.bits & 0x03) as u8)
100    }
101    #[doc = "Bits 2:7 - General Purpose Registers"]
102    #[inline(always)]
103    pub fn scratch0(&self) -> SCRATCH0_R {
104        SCRATCH0_R::new(((self.bits >> 2) & 0x3f) as u8)
105    }
106}
107impl W {
108    #[doc = "Bits 0:1 - AHB Memory Read Option \n 2'b11 : If MemAddrByte\\[1:0\\]
109is 2'b11, then AHB Memory Read will not be automatically triggered once MemAddrByte1 is written Other : The AHB Memory Read behavior is same as S2, Once MemAddrByte1 is written, AHB Memory read is triggered."]
110    #[inline(always)]
111    pub fn ahb_read_req_mode(&mut self) -> AHBREADREQMODE_W {
112        AHBREADREQMODE_W { w: self }
113    }
114    #[doc = "Bits 2:7 - General Purpose Registers"]
115    #[inline(always)]
116    pub fn scratch0(&mut self) -> SCRATCH0_W {
117        SCRATCH0_W { w: self }
118    }
119    #[doc = "Writes raw bits to the register."]
120    #[inline(always)]
121    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
122        self.0.bits(bits);
123        self
124    }
125}
126#[doc = "AHB access control register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ahbaccessctl](index.html) module"]
127pub struct AHBACCESSCTL_SPEC;
128impl crate::RegisterSpec for AHBACCESSCTL_SPEC {
129    type Ux = u8;
130}
131#[doc = "`read()` method returns [ahbaccessctl::R](R) reader structure"]
132impl crate::Readable for AHBACCESSCTL_SPEC {
133    type Reader = R;
134}
135#[doc = "`write(|w| ..)` method takes [ahbaccessctl::W](W) writer structure"]
136impl crate::Writable for AHBACCESSCTL_SPEC {
137    type Writer = W;
138}
139#[doc = "`reset()` method sets AHBACCESSCTL to value 0"]
140impl crate::Resettable for AHBACCESSCTL_SPEC {
141    #[inline(always)]
142    fn reset_value() -> Self::Ux {
143        0
144    }
145}
eos_s3/spi_tlc/ahbaccessctl.rs

eos_s3/spi_tlc/
ahbaccessctl.rs
