1#[doc = "Register `SR` reader"]
2pub struct R(crate::R<SR_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SR_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SR_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SR_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Field `BUSY` reader - SSI Busy Flag. When set, indicates that a serial transfer is in progress; when cleared indicates that the SPI Master is idle or disabled."]
17pub struct BUSY_R(crate::FieldReader<bool, bool>);
18impl BUSY_R {
19 #[inline(always)]
20 pub(crate) fn new(bits: bool) -> Self {
21 BUSY_R(crate::FieldReader::new(bits))
22 }
23}
24impl core::ops::Deref for BUSY_R {
25 type Target = crate::FieldReader<bool, bool>;
26 #[inline(always)]
27 fn deref(&self) -> &Self::Target {
28 &self.0
29 }
30}
31#[doc = "Field `TFNF` reader - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full."]
32pub struct TFNF_R(crate::FieldReader<bool, bool>);
33impl TFNF_R {
34 #[inline(always)]
35 pub(crate) fn new(bits: bool) -> Self {
36 TFNF_R(crate::FieldReader::new(bits))
37 }
38}
39impl core::ops::Deref for TFNF_R {
40 type Target = crate::FieldReader<bool, bool>;
41 #[inline(always)]
42 fn deref(&self) -> &Self::Target {
43 &self.0
44 }
45}
46#[doc = "Field `TFE` reader - Transmit FIFO Empty. When the transmit FIFO is completely empty, this bit is set. When the transmit FIFO contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt."]
47pub struct TFE_R(crate::FieldReader<bool, bool>);
48impl TFE_R {
49 #[inline(always)]
50 pub(crate) fn new(bits: bool) -> Self {
51 TFE_R(crate::FieldReader::new(bits))
52 }
53}
54impl core::ops::Deref for TFE_R {
55 type Target = crate::FieldReader<bool, bool>;
56 #[inline(always)]
57 fn deref(&self) -> &Self::Target {
58 &self.0
59 }
60}
61#[doc = "Field `RFNE` reader - Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO."]
62pub struct RFNE_R(crate::FieldReader<bool, bool>);
63impl RFNE_R {
64 #[inline(always)]
65 pub(crate) fn new(bits: bool) -> Self {
66 RFNE_R(crate::FieldReader::new(bits))
67 }
68}
69impl core::ops::Deref for RFNE_R {
70 type Target = crate::FieldReader<bool, bool>;
71 #[inline(always)]
72 fn deref(&self) -> &Self::Target {
73 &self.0
74 }
75}
76#[doc = "Field `RFF` reader - Receive FIFO Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared."]
77pub struct RFF_R(crate::FieldReader<bool, bool>);
78impl RFF_R {
79 #[inline(always)]
80 pub(crate) fn new(bits: bool) -> Self {
81 RFF_R(crate::FieldReader::new(bits))
82 }
83}
84impl core::ops::Deref for RFF_R {
85 type Target = crate::FieldReader<bool, bool>;
86 #[inline(always)]
87 fn deref(&self) -> &Self::Target {
88 &self.0
89 }
90}
91#[doc = "Field `TXE` reader - No function for SPI Master. Slave usage only."]
92pub struct TXE_R(crate::FieldReader<bool, bool>);
93impl TXE_R {
94 #[inline(always)]
95 pub(crate) fn new(bits: bool) -> Self {
96 TXE_R(crate::FieldReader::new(bits))
97 }
98}
99impl core::ops::Deref for TXE_R {
100 type Target = crate::FieldReader<bool, bool>;
101 #[inline(always)]
102 fn deref(&self) -> &Self::Target {
103 &self.0
104 }
105}
106#[doc = "Field `DCOL` reader - Data Collision Error. Relevant only when the SPI Master is configured as a master device. This bit is set if the SPI Master is actively transmitting when another master selects this device as a slave. This informs the processor that the last data transfer was halted before completion. This bit is cleared when read."]
107pub struct DCOL_R(crate::FieldReader<bool, bool>);
108impl DCOL_R {
109 #[inline(always)]
110 pub(crate) fn new(bits: bool) -> Self {
111 DCOL_R(crate::FieldReader::new(bits))
112 }
113}
114impl core::ops::Deref for DCOL_R {
115 type Target = crate::FieldReader<bool, bool>;
116 #[inline(always)]
117 fn deref(&self) -> &Self::Target {
118 &self.0
119 }
120}
121impl R {
122 #[doc = "Bit 0 - SSI Busy Flag. When set, indicates that a serial transfer is in progress; when cleared indicates that the SPI Master is idle or disabled."]
123 #[inline(always)]
124 pub fn busy(&self) -> BUSY_R {
125 BUSY_R::new((self.bits & 0x01) != 0)
126 }
127 #[doc = "Bit 1 - Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full."]
128 #[inline(always)]
129 pub fn tfnf(&self) -> TFNF_R {
130 TFNF_R::new(((self.bits >> 1) & 0x01) != 0)
131 }
132 #[doc = "Bit 2 - Transmit FIFO Empty. When the transmit FIFO is completely empty, this bit is set. When the transmit FIFO contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt."]
133 #[inline(always)]
134 pub fn tfe(&self) -> TFE_R {
135 TFE_R::new(((self.bits >> 2) & 0x01) != 0)
136 }
137 #[doc = "Bit 3 - Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO."]
138 #[inline(always)]
139 pub fn rfne(&self) -> RFNE_R {
140 RFNE_R::new(((self.bits >> 3) & 0x01) != 0)
141 }
142 #[doc = "Bit 4 - Receive FIFO Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared."]
143 #[inline(always)]
144 pub fn rff(&self) -> RFF_R {
145 RFF_R::new(((self.bits >> 4) & 0x01) != 0)
146 }
147 #[doc = "Bit 5 - No function for SPI Master. Slave usage only."]
148 #[inline(always)]
149 pub fn txe(&self) -> TXE_R {
150 TXE_R::new(((self.bits >> 5) & 0x01) != 0)
151 }
152 #[doc = "Bit 6 - Data Collision Error. Relevant only when the SPI Master is configured as a master device. This bit is set if the SPI Master is actively transmitting when another master selects this device as a slave. This informs the processor that the last data transfer was halted before completion. This bit is cleared when read."]
153 #[inline(always)]
154 pub fn dcol(&self) -> DCOL_R {
155 DCOL_R::new(((self.bits >> 6) & 0x01) != 0)
156 }
157}
158#[doc = "Status Register: This is a read-only register used to indicate the current transfer status, FIFO status, and any transmission/reception errors that may have occurred. This status register may be read at any time. None of the bits in this register request an interrupt.\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sr](index.html) module"]
159pub struct SR_SPEC;
160impl crate::RegisterSpec for SR_SPEC {
161 type Ux = u8;
162}
163#[doc = "`read()` method returns [sr::R](R) reader structure"]
164impl crate::Readable for SR_SPEC {
165 type Reader = R;
166}
167#[doc = "`reset()` method sets SR to value 0"]
168impl crate::Resettable for SR_SPEC {
169 #[inline(always)]
170 fn reset_value() -> Self::Ux {
171 0
172 }
173}