eos_s3/sdma_sram/
ch_cfg_ch3.rs

1#[doc = "Register `CH_CFG_CH3` reader"]
2pub struct R(crate::R<CH_CFG_CH3_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CH_CFG_CH3_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CH_CFG_CH3_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CH_CFG_CH3_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CH_CFG_CH3` writer"]
17pub struct W(crate::W<CH_CFG_CH3_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CH_CFG_CH3_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CH_CFG_CH3_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CH_CFG_CH3_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `cycle_ctrl` reader - The operating mode of the DMA cycle"]
38pub struct CYCLE_CTRL_R(crate::FieldReader<u8, u8>);
39impl CYCLE_CTRL_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: u8) -> Self {
42        CYCLE_CTRL_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for CYCLE_CTRL_R {
46    type Target = crate::FieldReader<u8, u8>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `cycle_ctrl` writer - The operating mode of the DMA cycle"]
53pub struct CYCLE_CTRL_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> CYCLE_CTRL_W<'a> {
57    #[doc = r"Writes raw bits to the field"]
58    #[inline(always)]
59    pub unsafe fn bits(self, value: u8) -> &'a mut W {
60        self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
61        self.w
62    }
63}
64#[doc = "Field `next_useburst` reader - Controls if the chnl_useburst_set \\[C\\]
65bit is set to a 1, when the controller is performing a peripheral scatter-gather and is completing a DMA cycle that uses the alternate data structure"]
66pub struct NEXT_USEBURST_R(crate::FieldReader<bool, bool>);
67impl NEXT_USEBURST_R {
68    #[inline(always)]
69    pub(crate) fn new(bits: bool) -> Self {
70        NEXT_USEBURST_R(crate::FieldReader::new(bits))
71    }
72}
73impl core::ops::Deref for NEXT_USEBURST_R {
74    type Target = crate::FieldReader<bool, bool>;
75    #[inline(always)]
76    fn deref(&self) -> &Self::Target {
77        &self.0
78    }
79}
80#[doc = "Field `next_useburst` writer - Controls if the chnl_useburst_set \\[C\\]
81bit is set to a 1, when the controller is performing a peripheral scatter-gather and is completing a DMA cycle that uses the alternate data structure"]
82pub struct NEXT_USEBURST_W<'a> {
83    w: &'a mut W,
84}
85impl<'a> NEXT_USEBURST_W<'a> {
86    #[doc = r"Sets the field bit"]
87    #[inline(always)]
88    pub fn set_bit(self) -> &'a mut W {
89        self.bit(true)
90    }
91    #[doc = r"Clears the field bit"]
92    #[inline(always)]
93    pub fn clear_bit(self) -> &'a mut W {
94        self.bit(false)
95    }
96    #[doc = r"Writes raw bits to the field"]
97    #[inline(always)]
98    pub fn bit(self, value: bool) -> &'a mut W {
99        self.w.bits =
100            (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
101        self.w
102    }
103}
104#[doc = "Field `n_minus_1` reader - Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers that the DMA cycle contains. You must set these bits according to the size of DMA cycle that you require."]
105pub struct N_MINUS_1_R(crate::FieldReader<u16, u16>);
106impl N_MINUS_1_R {
107    #[inline(always)]
108    pub(crate) fn new(bits: u16) -> Self {
109        N_MINUS_1_R(crate::FieldReader::new(bits))
110    }
111}
112impl core::ops::Deref for N_MINUS_1_R {
113    type Target = crate::FieldReader<u16, u16>;
114    #[inline(always)]
115    fn deref(&self) -> &Self::Target {
116        &self.0
117    }
118}
119#[doc = "Field `n_minus_1` writer - Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers that the DMA cycle contains. You must set these bits according to the size of DMA cycle that you require."]
120pub struct N_MINUS_1_W<'a> {
121    w: &'a mut W,
122}
123impl<'a> N_MINUS_1_W<'a> {
124    #[doc = r"Writes raw bits to the field"]
125    #[inline(always)]
126    pub unsafe fn bits(self, value: u16) -> &'a mut W {
127        self.w.bits =
128            (self.w.bits & !(0x03ff << 4)) | ((value as u32 & 0x03ff) << 4);
129        self.w
130    }
131}
132#[doc = "Field `R_power` reader - Set these bits to control how many DMA transfers can occur before the controller rearbitrates"]
133pub struct R_POWER_R(crate::FieldReader<u8, u8>);
134impl R_POWER_R {
135    #[inline(always)]
136    pub(crate) fn new(bits: u8) -> Self {
137        R_POWER_R(crate::FieldReader::new(bits))
138    }
139}
140impl core::ops::Deref for R_POWER_R {
141    type Target = crate::FieldReader<u8, u8>;
142    #[inline(always)]
143    fn deref(&self) -> &Self::Target {
144        &self.0
145    }
146}
147#[doc = "Field `R_power` writer - Set these bits to control how many DMA transfers can occur before the controller rearbitrates"]
148pub struct R_POWER_W<'a> {
149    w: &'a mut W,
150}
151impl<'a> R_POWER_W<'a> {
152    #[doc = r"Writes raw bits to the field"]
153    #[inline(always)]
154    pub unsafe fn bits(self, value: u8) -> &'a mut W {
155        self.w.bits =
156            (self.w.bits & !(0x0f << 14)) | ((value as u32 & 0x0f) << 14);
157        self.w
158    }
159}
160#[doc = "Field `src_prot_ctrl` reader - Set the bits to control the state of HPROT\\[3:1\\]
161when the controller reads the source data"]
162pub struct SRC_PROT_CTRL_R(crate::FieldReader<u8, u8>);
163impl SRC_PROT_CTRL_R {
164    #[inline(always)]
165    pub(crate) fn new(bits: u8) -> Self {
166        SRC_PROT_CTRL_R(crate::FieldReader::new(bits))
167    }
168}
169impl core::ops::Deref for SRC_PROT_CTRL_R {
170    type Target = crate::FieldReader<u8, u8>;
171    #[inline(always)]
172    fn deref(&self) -> &Self::Target {
173        &self.0
174    }
175}
176#[doc = "Field `src_prot_ctrl` writer - Set the bits to control the state of HPROT\\[3:1\\]
177when the controller reads the source data"]
178pub struct SRC_PROT_CTRL_W<'a> {
179    w: &'a mut W,
180}
181impl<'a> SRC_PROT_CTRL_W<'a> {
182    #[doc = r"Writes raw bits to the field"]
183    #[inline(always)]
184    pub unsafe fn bits(self, value: u8) -> &'a mut W {
185        self.w.bits =
186            (self.w.bits & !(0x07 << 18)) | ((value as u32 & 0x07) << 18);
187        self.w
188    }
189}
190#[doc = "Field `dst_prot_ctrl` reader - Set the bits to control the state of HPROT\\[3:1\\]
191when the controller writes the destination data"]
192pub struct DST_PROT_CTRL_R(crate::FieldReader<u8, u8>);
193impl DST_PROT_CTRL_R {
194    #[inline(always)]
195    pub(crate) fn new(bits: u8) -> Self {
196        DST_PROT_CTRL_R(crate::FieldReader::new(bits))
197    }
198}
199impl core::ops::Deref for DST_PROT_CTRL_R {
200    type Target = crate::FieldReader<u8, u8>;
201    #[inline(always)]
202    fn deref(&self) -> &Self::Target {
203        &self.0
204    }
205}
206#[doc = "Field `dst_prot_ctrl` writer - Set the bits to control the state of HPROT\\[3:1\\]
207when the controller writes the destination data"]
208pub struct DST_PROT_CTRL_W<'a> {
209    w: &'a mut W,
210}
211impl<'a> DST_PROT_CTRL_W<'a> {
212    #[doc = r"Writes raw bits to the field"]
213    #[inline(always)]
214    pub unsafe fn bits(self, value: u8) -> &'a mut W {
215        self.w.bits =
216            (self.w.bits & !(0x07 << 21)) | ((value as u32 & 0x07) << 21);
217        self.w
218    }
219}
220#[doc = "Field `src_size` reader - Source data size"]
221pub struct SRC_SIZE_R(crate::FieldReader<u8, u8>);
222impl SRC_SIZE_R {
223    #[inline(always)]
224    pub(crate) fn new(bits: u8) -> Self {
225        SRC_SIZE_R(crate::FieldReader::new(bits))
226    }
227}
228impl core::ops::Deref for SRC_SIZE_R {
229    type Target = crate::FieldReader<u8, u8>;
230    #[inline(always)]
231    fn deref(&self) -> &Self::Target {
232        &self.0
233    }
234}
235#[doc = "Field `src_size` writer - Source data size"]
236pub struct SRC_SIZE_W<'a> {
237    w: &'a mut W,
238}
239impl<'a> SRC_SIZE_W<'a> {
240    #[doc = r"Writes raw bits to the field"]
241    #[inline(always)]
242    pub unsafe fn bits(self, value: u8) -> &'a mut W {
243        self.w.bits =
244            (self.w.bits & !(0x03 << 24)) | ((value as u32 & 0x03) << 24);
245        self.w
246    }
247}
248#[doc = "Field `src_inc` reader - Source address increment"]
249pub struct SRC_INC_R(crate::FieldReader<u8, u8>);
250impl SRC_INC_R {
251    #[inline(always)]
252    pub(crate) fn new(bits: u8) -> Self {
253        SRC_INC_R(crate::FieldReader::new(bits))
254    }
255}
256impl core::ops::Deref for SRC_INC_R {
257    type Target = crate::FieldReader<u8, u8>;
258    #[inline(always)]
259    fn deref(&self) -> &Self::Target {
260        &self.0
261    }
262}
263#[doc = "Field `src_inc` writer - Source address increment"]
264pub struct SRC_INC_W<'a> {
265    w: &'a mut W,
266}
267impl<'a> SRC_INC_W<'a> {
268    #[doc = r"Writes raw bits to the field"]
269    #[inline(always)]
270    pub unsafe fn bits(self, value: u8) -> &'a mut W {
271        self.w.bits =
272            (self.w.bits & !(0x03 << 26)) | ((value as u32 & 0x03) << 26);
273        self.w
274    }
275}
276#[doc = "Field `dst_size` reader - Destination data size"]
277pub struct DST_SIZE_R(crate::FieldReader<u8, u8>);
278impl DST_SIZE_R {
279    #[inline(always)]
280    pub(crate) fn new(bits: u8) -> Self {
281        DST_SIZE_R(crate::FieldReader::new(bits))
282    }
283}
284impl core::ops::Deref for DST_SIZE_R {
285    type Target = crate::FieldReader<u8, u8>;
286    #[inline(always)]
287    fn deref(&self) -> &Self::Target {
288        &self.0
289    }
290}
291#[doc = "Field `dst_size` writer - Destination data size"]
292pub struct DST_SIZE_W<'a> {
293    w: &'a mut W,
294}
295impl<'a> DST_SIZE_W<'a> {
296    #[doc = r"Writes raw bits to the field"]
297    #[inline(always)]
298    pub unsafe fn bits(self, value: u8) -> &'a mut W {
299        self.w.bits =
300            (self.w.bits & !(0x03 << 28)) | ((value as u32 & 0x03) << 28);
301        self.w
302    }
303}
304#[doc = "Field `dst_inc` reader - Destination address increment"]
305pub struct DST_INC_R(crate::FieldReader<u8, u8>);
306impl DST_INC_R {
307    #[inline(always)]
308    pub(crate) fn new(bits: u8) -> Self {
309        DST_INC_R(crate::FieldReader::new(bits))
310    }
311}
312impl core::ops::Deref for DST_INC_R {
313    type Target = crate::FieldReader<u8, u8>;
314    #[inline(always)]
315    fn deref(&self) -> &Self::Target {
316        &self.0
317    }
318}
319#[doc = "Field `dst_inc` writer - Destination address increment"]
320pub struct DST_INC_W<'a> {
321    w: &'a mut W,
322}
323impl<'a> DST_INC_W<'a> {
324    #[doc = r"Writes raw bits to the field"]
325    #[inline(always)]
326    pub unsafe fn bits(self, value: u8) -> &'a mut W {
327        self.w.bits =
328            (self.w.bits & !(0x03 << 30)) | ((value as u32 & 0x03) << 30);
329        self.w
330    }
331}
332impl R {
333    #[doc = "Bits 0:2 - The operating mode of the DMA cycle"]
334    #[inline(always)]
335    pub fn cycle_ctrl(&self) -> CYCLE_CTRL_R {
336        CYCLE_CTRL_R::new((self.bits & 0x07) as u8)
337    }
338    #[doc = "Bit 3 - Controls if the chnl_useburst_set \\[C\\]
339bit is set to a 1, when the controller is performing a peripheral scatter-gather and is completing a DMA cycle that uses the alternate data structure"]
340    #[inline(always)]
341    pub fn next_useburst(&self) -> NEXT_USEBURST_R {
342        NEXT_USEBURST_R::new(((self.bits >> 3) & 0x01) != 0)
343    }
344    #[doc = "Bits 4:13 - Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers that the DMA cycle contains. You must set these bits according to the size of DMA cycle that you require."]
345    #[inline(always)]
346    pub fn n_minus_1(&self) -> N_MINUS_1_R {
347        N_MINUS_1_R::new(((self.bits >> 4) & 0x03ff) as u16)
348    }
349    #[doc = "Bits 14:17 - Set these bits to control how many DMA transfers can occur before the controller rearbitrates"]
350    #[inline(always)]
351    pub fn r_power(&self) -> R_POWER_R {
352        R_POWER_R::new(((self.bits >> 14) & 0x0f) as u8)
353    }
354    #[doc = "Bits 18:20 - Set the bits to control the state of HPROT\\[3:1\\]
355when the controller reads the source data"]
356    #[inline(always)]
357    pub fn src_prot_ctrl(&self) -> SRC_PROT_CTRL_R {
358        SRC_PROT_CTRL_R::new(((self.bits >> 18) & 0x07) as u8)
359    }
360    #[doc = "Bits 21:23 - Set the bits to control the state of HPROT\\[3:1\\]
361when the controller writes the destination data"]
362    #[inline(always)]
363    pub fn dst_prot_ctrl(&self) -> DST_PROT_CTRL_R {
364        DST_PROT_CTRL_R::new(((self.bits >> 21) & 0x07) as u8)
365    }
366    #[doc = "Bits 24:25 - Source data size"]
367    #[inline(always)]
368    pub fn src_size(&self) -> SRC_SIZE_R {
369        SRC_SIZE_R::new(((self.bits >> 24) & 0x03) as u8)
370    }
371    #[doc = "Bits 26:27 - Source address increment"]
372    #[inline(always)]
373    pub fn src_inc(&self) -> SRC_INC_R {
374        SRC_INC_R::new(((self.bits >> 26) & 0x03) as u8)
375    }
376    #[doc = "Bits 28:29 - Destination data size"]
377    #[inline(always)]
378    pub fn dst_size(&self) -> DST_SIZE_R {
379        DST_SIZE_R::new(((self.bits >> 28) & 0x03) as u8)
380    }
381    #[doc = "Bits 30:31 - Destination address increment"]
382    #[inline(always)]
383    pub fn dst_inc(&self) -> DST_INC_R {
384        DST_INC_R::new(((self.bits >> 30) & 0x03) as u8)
385    }
386}
387impl W {
388    #[doc = "Bits 0:2 - The operating mode of the DMA cycle"]
389    #[inline(always)]
390    pub fn cycle_ctrl(&mut self) -> CYCLE_CTRL_W {
391        CYCLE_CTRL_W { w: self }
392    }
393    #[doc = "Bit 3 - Controls if the chnl_useburst_set \\[C\\]
394bit is set to a 1, when the controller is performing a peripheral scatter-gather and is completing a DMA cycle that uses the alternate data structure"]
395    #[inline(always)]
396    pub fn next_useburst(&mut self) -> NEXT_USEBURST_W {
397        NEXT_USEBURST_W { w: self }
398    }
399    #[doc = "Bits 4:13 - Prior to the DMA cycle commencing, these bits represent the total number of DMA transfers that the DMA cycle contains. You must set these bits according to the size of DMA cycle that you require."]
400    #[inline(always)]
401    pub fn n_minus_1(&mut self) -> N_MINUS_1_W {
402        N_MINUS_1_W { w: self }
403    }
404    #[doc = "Bits 14:17 - Set these bits to control how many DMA transfers can occur before the controller rearbitrates"]
405    #[inline(always)]
406    pub fn r_power(&mut self) -> R_POWER_W {
407        R_POWER_W { w: self }
408    }
409    #[doc = "Bits 18:20 - Set the bits to control the state of HPROT\\[3:1\\]
410when the controller reads the source data"]
411    #[inline(always)]
412    pub fn src_prot_ctrl(&mut self) -> SRC_PROT_CTRL_W {
413        SRC_PROT_CTRL_W { w: self }
414    }
415    #[doc = "Bits 21:23 - Set the bits to control the state of HPROT\\[3:1\\]
416when the controller writes the destination data"]
417    #[inline(always)]
418    pub fn dst_prot_ctrl(&mut self) -> DST_PROT_CTRL_W {
419        DST_PROT_CTRL_W { w: self }
420    }
421    #[doc = "Bits 24:25 - Source data size"]
422    #[inline(always)]
423    pub fn src_size(&mut self) -> SRC_SIZE_W {
424        SRC_SIZE_W { w: self }
425    }
426    #[doc = "Bits 26:27 - Source address increment"]
427    #[inline(always)]
428    pub fn src_inc(&mut self) -> SRC_INC_W {
429        SRC_INC_W { w: self }
430    }
431    #[doc = "Bits 28:29 - Destination data size"]
432    #[inline(always)]
433    pub fn dst_size(&mut self) -> DST_SIZE_W {
434        DST_SIZE_W { w: self }
435    }
436    #[doc = "Bits 30:31 - Destination address increment"]
437    #[inline(always)]
438    pub fn dst_inc(&mut self) -> DST_INC_W {
439        DST_INC_W { w: self }
440    }
441    #[doc = "Writes raw bits to the register."]
442    #[inline(always)]
443    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
444        self.0.bits(bits);
445        self
446    }
447}
448#[doc = "Primary configuration for channel 3\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ch_cfg_ch3](index.html) module"]
449pub struct CH_CFG_CH3_SPEC;
450impl crate::RegisterSpec for CH_CFG_CH3_SPEC {
451    type Ux = u32;
452}
453#[doc = "`read()` method returns [ch_cfg_ch3::R](R) reader structure"]
454impl crate::Readable for CH_CFG_CH3_SPEC {
455    type Reader = R;
456}
457#[doc = "`write(|w| ..)` method takes [ch_cfg_ch3::W](W) writer structure"]
458impl crate::Writable for CH_CFG_CH3_SPEC {
459    type Writer = W;
460}
461#[doc = "`reset()` method sets CH_CFG_CH3 to value 0"]
462impl crate::Resettable for CH_CFG_CH3_SPEC {
463    #[inline(always)]
464    fn reset_value() -> Self::Ux {
465        0
466    }
467}
eos_s3/sdma_sram/ch_cfg_ch3.rs

eos_s3/sdma_sram/
ch_cfg_ch3.rs
