eos_s3/sdma/
dma_status.rs

1#[doc = "Register `DMA_STATUS` reader"]
2pub struct R(crate::R<DMA_STATUS_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DMA_STATUS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DMA_STATUS_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DMA_STATUS_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Field `master_enable` reader - Set if controller is enabled"]
17pub struct MASTER_ENABLE_R(crate::FieldReader<bool, bool>);
18impl MASTER_ENABLE_R {
19    #[inline(always)]
20    pub(crate) fn new(bits: bool) -> Self {
21        MASTER_ENABLE_R(crate::FieldReader::new(bits))
22    }
23}
24impl core::ops::Deref for MASTER_ENABLE_R {
25    type Target = crate::FieldReader<bool, bool>;
26    #[inline(always)]
27    fn deref(&self) -> &Self::Target {
28        &self.0
29    }
30}
31#[doc = "Current state of the control state machine.\n\nValue on reset: 0"]
32#[derive(Clone, Copy, Debug, PartialEq)]
33#[repr(u8)]
34pub enum STATE_A {
35    #[doc = "0: idle state"]
36    IDLE = 0,
37    #[doc = "1: reading channel controller data."]
38    READ_CH_CNTRL_DATA = 1,
39    #[doc = "2: reading source data end pointer"]
40    READ_SRC_DATA_END_PTR = 2,
41    #[doc = "3: reading destination data end pointer"]
42    READ_DEST_DATA_END_PTR = 3,
43    #[doc = "4: reading source data"]
44    READ_SRC_DATA = 4,
45    #[doc = "5: writing destination data"]
46    WRITE_DEST_DATA = 5,
47    #[doc = "6: waiting for DMA request to clear"]
48    WAIT_DMA_REQ_CLEAR = 6,
49    #[doc = "7: writing channel controller data"]
50    WRITE_CH_CTRL_DATA = 7,
51    #[doc = "8: stalled state"]
52    STALLED = 8,
53    #[doc = "9: done state"]
54    DONE = 9,
55    #[doc = "10: peripheral scatter-gather transition"]
56    PERIPH_SCATTER_GATHER_TRANS = 10,
57}
58impl From<STATE_A> for u8 {
59    #[inline(always)]
60    fn from(variant: STATE_A) -> Self {
61        variant as _
62    }
63}
64#[doc = "Field `state` reader - Current state of the control state machine."]
65pub struct STATE_R(crate::FieldReader<u8, STATE_A>);
66impl STATE_R {
67    #[inline(always)]
68    pub(crate) fn new(bits: u8) -> Self {
69        STATE_R(crate::FieldReader::new(bits))
70    }
71    #[doc = r"Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> Option<STATE_A> {
74        match self.bits {
75            0 => Some(STATE_A::IDLE),
76            1 => Some(STATE_A::READ_CH_CNTRL_DATA),
77            2 => Some(STATE_A::READ_SRC_DATA_END_PTR),
78            3 => Some(STATE_A::READ_DEST_DATA_END_PTR),
79            4 => Some(STATE_A::READ_SRC_DATA),
80            5 => Some(STATE_A::WRITE_DEST_DATA),
81            6 => Some(STATE_A::WAIT_DMA_REQ_CLEAR),
82            7 => Some(STATE_A::WRITE_CH_CTRL_DATA),
83            8 => Some(STATE_A::STALLED),
84            9 => Some(STATE_A::DONE),
85            10 => Some(STATE_A::PERIPH_SCATTER_GATHER_TRANS),
86            _ => None,
87        }
88    }
89    #[doc = "Checks if the value of the field is `IDLE`"]
90    #[inline(always)]
91    pub fn is_idle(&self) -> bool {
92        **self == STATE_A::IDLE
93    }
94    #[doc = "Checks if the value of the field is `READ_CH_CNTRL_DATA`"]
95    #[inline(always)]
96    pub fn is_read_ch_cntrl_data(&self) -> bool {
97        **self == STATE_A::READ_CH_CNTRL_DATA
98    }
99    #[doc = "Checks if the value of the field is `READ_SRC_DATA_END_PTR`"]
100    #[inline(always)]
101    pub fn is_read_src_data_end_ptr(&self) -> bool {
102        **self == STATE_A::READ_SRC_DATA_END_PTR
103    }
104    #[doc = "Checks if the value of the field is `READ_DEST_DATA_END_PTR`"]
105    #[inline(always)]
106    pub fn is_read_dest_data_end_ptr(&self) -> bool {
107        **self == STATE_A::READ_DEST_DATA_END_PTR
108    }
109    #[doc = "Checks if the value of the field is `READ_SRC_DATA`"]
110    #[inline(always)]
111    pub fn is_read_src_data(&self) -> bool {
112        **self == STATE_A::READ_SRC_DATA
113    }
114    #[doc = "Checks if the value of the field is `WRITE_DEST_DATA`"]
115    #[inline(always)]
116    pub fn is_write_dest_data(&self) -> bool {
117        **self == STATE_A::WRITE_DEST_DATA
118    }
119    #[doc = "Checks if the value of the field is `WAIT_DMA_REQ_CLEAR`"]
120    #[inline(always)]
121    pub fn is_wait_dma_req_clear(&self) -> bool {
122        **self == STATE_A::WAIT_DMA_REQ_CLEAR
123    }
124    #[doc = "Checks if the value of the field is `WRITE_CH_CTRL_DATA`"]
125    #[inline(always)]
126    pub fn is_write_ch_ctrl_data(&self) -> bool {
127        **self == STATE_A::WRITE_CH_CTRL_DATA
128    }
129    #[doc = "Checks if the value of the field is `STALLED`"]
130    #[inline(always)]
131    pub fn is_stalled(&self) -> bool {
132        **self == STATE_A::STALLED
133    }
134    #[doc = "Checks if the value of the field is `DONE`"]
135    #[inline(always)]
136    pub fn is_done(&self) -> bool {
137        **self == STATE_A::DONE
138    }
139    #[doc = "Checks if the value of the field is `PERIPH_SCATTER_GATHER_TRANS`"]
140    #[inline(always)]
141    pub fn is_periph_scatter_gather_trans(&self) -> bool {
142        **self == STATE_A::PERIPH_SCATTER_GATHER_TRANS
143    }
144}
145impl core::ops::Deref for STATE_R {
146    type Target = crate::FieldReader<u8, STATE_A>;
147    #[inline(always)]
148    fn deref(&self) -> &Self::Target {
149        &self.0
150    }
151}
152#[doc = "Field `chnls_minus1` reader - Number of available DMA channels (value in register + 1)"]
153pub struct CHNLS_MINUS1_R(crate::FieldReader<u8, u8>);
154impl CHNLS_MINUS1_R {
155    #[inline(always)]
156    pub(crate) fn new(bits: u8) -> Self {
157        CHNLS_MINUS1_R(crate::FieldReader::new(bits))
158    }
159}
160impl core::ops::Deref for CHNLS_MINUS1_R {
161    type Target = crate::FieldReader<u8, u8>;
162    #[inline(always)]
163    fn deref(&self) -> &Self::Target {
164        &self.0
165    }
166}
167#[doc = "Field `test_status` reader - To reduce the gate count you can configure the controller to exclude the integration test logic. If value = 1, the integration test logic is included. If 0, test logic is not included. Any other value is undefined"]
168pub struct TEST_STATUS_R(crate::FieldReader<u8, u8>);
169impl TEST_STATUS_R {
170    #[inline(always)]
171    pub(crate) fn new(bits: u8) -> Self {
172        TEST_STATUS_R(crate::FieldReader::new(bits))
173    }
174}
175impl core::ops::Deref for TEST_STATUS_R {
176    type Target = crate::FieldReader<u8, u8>;
177    #[inline(always)]
178    fn deref(&self) -> &Self::Target {
179        &self.0
180    }
181}
182impl R {
183    #[doc = "Bit 0 - Set if controller is enabled"]
184    #[inline(always)]
185    pub fn master_enable(&self) -> MASTER_ENABLE_R {
186        MASTER_ENABLE_R::new((self.bits & 0x01) != 0)
187    }
188    #[doc = "Bits 4:7 - Current state of the control state machine."]
189    #[inline(always)]
190    pub fn state(&self) -> STATE_R {
191        STATE_R::new(((self.bits >> 4) & 0x0f) as u8)
192    }
193    #[doc = "Bits 16:20 - Number of available DMA channels (value in register + 1)"]
194    #[inline(always)]
195    pub fn chnls_minus1(&self) -> CHNLS_MINUS1_R {
196        CHNLS_MINUS1_R::new(((self.bits >> 16) & 0x1f) as u8)
197    }
198    #[doc = "Bits 28:31 - To reduce the gate count you can configure the controller to exclude the integration test logic. If value = 1, the integration test logic is included. If 0, test logic is not included. Any other value is undefined"]
199    #[inline(always)]
200    pub fn test_status(&self) -> TEST_STATUS_R {
201        TEST_STATUS_R::new(((self.bits >> 28) & 0x0f) as u8)
202    }
203}
204#[doc = "DMA Status register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_status](index.html) module"]
205pub struct DMA_STATUS_SPEC;
206impl crate::RegisterSpec for DMA_STATUS_SPEC {
207    type Ux = u32;
208}
209#[doc = "`read()` method returns [dma_status::R](R) reader structure"]
210impl crate::Readable for DMA_STATUS_SPEC {
211    type Reader = R;
212}
213#[doc = "`reset()` method sets DMA_STATUS to value 0x100f_0000"]
214impl crate::Resettable for DMA_STATUS_SPEC {
215    #[inline(always)]
216    fn reset_value() -> Self::Ux {
217        0x100f_0000
218    }
219}
eos_s3/sdma/dma_status.rs

eos_s3/sdma/
dma_status.rs
