eos_s3/sdma/
dma_cfg.rs

1#[doc = "Register `DMA_CFG` writer"]
2pub struct W(crate::W<DMA_CFG_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<DMA_CFG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<DMA_CFG_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<DMA_CFG_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `master_enable` writer - Set to enable the controller"]
23pub struct MASTER_ENABLE_W<'a> {
24    w: &'a mut W,
25}
26impl<'a> MASTER_ENABLE_W<'a> {
27    #[doc = r"Sets the field bit"]
28    #[inline(always)]
29    pub fn set_bit(self) -> &'a mut W {
30        self.bit(true)
31    }
32    #[doc = r"Clears the field bit"]
33    #[inline(always)]
34    pub fn clear_bit(self) -> &'a mut W {
35        self.bit(false)
36    }
37    #[doc = r"Writes raw bits to the field"]
38    #[inline(always)]
39    pub fn bit(self, value: bool) -> &'a mut W {
40        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
41        self.w
42    }
43}
44#[doc = "Field `chnl_prot_ctrl` writer - Sets the AHB-Lite protection by controlling the HPROT\\[3:1\\]
45signal levels as follows: \n \n Bit \\[7\\]
46Controls HPROT\\[3\\]
47to indicate if a cacheable access is occurring. \n \n Bit \\[6\\]
48Controls HPROT\\[2\\]
49to indicate if a bufferable access is occurring. \n \n Bit \\[5\\]
50Controls HPROT\\[1\\]
51to indicate if a privileged access is occurring. \n \n Note\n \n When bit \\[n\\]
52= 1 then the corresponding HPROT is HIGH. \n \n When bit \\[n\\]
53= 0 then the corresponding HPROT is LOW."]
54pub struct CHNL_PROT_CTRL_W<'a> {
55    w: &'a mut W,
56}
57impl<'a> CHNL_PROT_CTRL_W<'a> {
58    #[doc = r"Writes raw bits to the field"]
59    #[inline(always)]
60    pub unsafe fn bits(self, value: u8) -> &'a mut W {
61        self.w.bits =
62            (self.w.bits & !(0x07 << 5)) | ((value as u32 & 0x07) << 5);
63        self.w
64    }
65}
66impl W {
67    #[doc = "Bit 0 - Set to enable the controller"]
68    #[inline(always)]
69    pub fn master_enable(&mut self) -> MASTER_ENABLE_W {
70        MASTER_ENABLE_W { w: self }
71    }
72    #[doc = "Bits 5:7 - Sets the AHB-Lite protection by controlling the HPROT\\[3:1\\]
73signal levels as follows: \n \n Bit \\[7\\]
74Controls HPROT\\[3\\]
75to indicate if a cacheable access is occurring. \n \n Bit \\[6\\]
76Controls HPROT\\[2\\]
77to indicate if a bufferable access is occurring. \n \n Bit \\[5\\]
78Controls HPROT\\[1\\]
79to indicate if a privileged access is occurring. \n \n Note\n \n When bit \\[n\\]
80= 1 then the corresponding HPROT is HIGH. \n \n When bit \\[n\\]
81= 0 then the corresponding HPROT is LOW."]
82    #[inline(always)]
83    pub fn chnl_prot_ctrl(&mut self) -> CHNL_PROT_CTRL_W {
84        CHNL_PROT_CTRL_W { w: self }
85    }
86    #[doc = "Writes raw bits to the register."]
87    #[inline(always)]
88    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
89        self.0.bits(bits);
90        self
91    }
92}
93#[doc = "DMA configuration register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma_cfg](index.html) module"]
94pub struct DMA_CFG_SPEC;
95impl crate::RegisterSpec for DMA_CFG_SPEC {
96    type Ux = u32;
97}
98#[doc = "`write(|w| ..)` method takes [dma_cfg::W](W) writer structure"]
99impl crate::Writable for DMA_CFG_SPEC {
100    type Writer = W;
101}
102#[doc = "`reset()` method sets DMA_CFG to value 0"]
103impl crate::Resettable for DMA_CFG_SPEC {
104    #[inline(always)]
105    fn reset_value() -> Self::Ux {
106        0
107    }
108}
eos_s3/sdma/dma_cfg.rs

eos_s3/sdma/
dma_cfg.rs
