eos_s3/sdma/
chnl_req_mask_set.rs

1#[doc = "Register `CHNL_REQ_MASK_SET` reader"]
2pub struct R(crate::R<CHNL_REQ_MASK_SET_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CHNL_REQ_MASK_SET_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CHNL_REQ_MASK_SET_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CHNL_REQ_MASK_SET_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CHNL_REQ_MASK_SET` writer"]
17pub struct W(crate::W<CHNL_REQ_MASK_SET_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CHNL_REQ_MASK_SET_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CHNL_REQ_MASK_SET_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CHNL_REQ_MASK_SET_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `chnl_req_mask_set` reader - Returns the request mask status of dma_req\\[C\\]
38and dma_sreq\\[C\\], or disables the corresponding channel from generating DMA requests. Read as: \n \n Bit \\[C\\]
39= 0 External requests are enabled for channel C. \n \n Bit \\[C\\]
40= 1 External requests are disabled for channel C. \n \n Write as: \n \n Bit \\[C\\]
41= 0 No effect. Use the chnl_req_mask_clr Register to enable DMA requests. \n Bit \\[C\\]
42= 1 Disables dma_req\\[C\\]
43and dma_sreq\\[C\\]
44from generating DMA requests. \n Writing to a bit where a DMA channel is not implemented has no effect."]
45pub struct CHNL_REQ_MASK_SET_R(crate::FieldReader<u16, u16>);
46impl CHNL_REQ_MASK_SET_R {
47    #[inline(always)]
48    pub(crate) fn new(bits: u16) -> Self {
49        CHNL_REQ_MASK_SET_R(crate::FieldReader::new(bits))
50    }
51}
52impl core::ops::Deref for CHNL_REQ_MASK_SET_R {
53    type Target = crate::FieldReader<u16, u16>;
54    #[inline(always)]
55    fn deref(&self) -> &Self::Target {
56        &self.0
57    }
58}
59#[doc = "Field `chnl_req_mask_set` writer - Returns the request mask status of dma_req\\[C\\]
60and dma_sreq\\[C\\], or disables the corresponding channel from generating DMA requests. Read as: \n \n Bit \\[C\\]
61= 0 External requests are enabled for channel C. \n \n Bit \\[C\\]
62= 1 External requests are disabled for channel C. \n \n Write as: \n \n Bit \\[C\\]
63= 0 No effect. Use the chnl_req_mask_clr Register to enable DMA requests. \n Bit \\[C\\]
64= 1 Disables dma_req\\[C\\]
65and dma_sreq\\[C\\]
66from generating DMA requests. \n Writing to a bit where a DMA channel is not implemented has no effect."]
67pub struct CHNL_REQ_MASK_SET_W<'a> {
68    w: &'a mut W,
69}
70impl<'a> CHNL_REQ_MASK_SET_W<'a> {
71    #[doc = r"Writes raw bits to the field"]
72    #[inline(always)]
73    pub unsafe fn bits(self, value: u16) -> &'a mut W {
74        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
75        self.w
76    }
77}
78impl R {
79    #[doc = "Bits 0:15 - Returns the request mask status of dma_req\\[C\\]
80and dma_sreq\\[C\\], or disables the corresponding channel from generating DMA requests. Read as: \n \n Bit \\[C\\]
81= 0 External requests are enabled for channel C. \n \n Bit \\[C\\]
82= 1 External requests are disabled for channel C. \n \n Write as: \n \n Bit \\[C\\]
83= 0 No effect. Use the chnl_req_mask_clr Register to enable DMA requests. \n Bit \\[C\\]
84= 1 Disables dma_req\\[C\\]
85and dma_sreq\\[C\\]
86from generating DMA requests. \n Writing to a bit where a DMA channel is not implemented has no effect."]
87    #[inline(always)]
88    pub fn chnl_req_mask_set(&self) -> CHNL_REQ_MASK_SET_R {
89        CHNL_REQ_MASK_SET_R::new((self.bits & 0xffff) as u16)
90    }
91}
92impl W {
93    #[doc = "Bits 0:15 - Returns the request mask status of dma_req\\[C\\]
94and dma_sreq\\[C\\], or disables the corresponding channel from generating DMA requests. Read as: \n \n Bit \\[C\\]
95= 0 External requests are enabled for channel C. \n \n Bit \\[C\\]
96= 1 External requests are disabled for channel C. \n \n Write as: \n \n Bit \\[C\\]
97= 0 No effect. Use the chnl_req_mask_clr Register to enable DMA requests. \n Bit \\[C\\]
98= 1 Disables dma_req\\[C\\]
99and dma_sreq\\[C\\]
100from generating DMA requests. \n Writing to a bit where a DMA channel is not implemented has no effect."]
101    #[inline(always)]
102    pub fn chnl_req_mask_set(&mut self) -> CHNL_REQ_MASK_SET_W {
103        CHNL_REQ_MASK_SET_W { w: self }
104    }
105    #[doc = "Writes raw bits to the register."]
106    #[inline(always)]
107    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
108        self.0.bits(bits);
109        self
110    }
111}
112#[doc = "Returns the request mask status of dma_req\\[\\]
113and dma_sreq\\[\\], or disables the corresponding channel from generating DMA requests.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_req_mask_set](index.html) module"]
114pub struct CHNL_REQ_MASK_SET_SPEC;
115impl crate::RegisterSpec for CHNL_REQ_MASK_SET_SPEC {
116    type Ux = u32;
117}
118#[doc = "`read()` method returns [chnl_req_mask_set::R](R) reader structure"]
119impl crate::Readable for CHNL_REQ_MASK_SET_SPEC {
120    type Reader = R;
121}
122#[doc = "`write(|w| ..)` method takes [chnl_req_mask_set::W](W) writer structure"]
123impl crate::Writable for CHNL_REQ_MASK_SET_SPEC {
124    type Writer = W;
125}
126#[doc = "`reset()` method sets CHNL_REQ_MASK_SET to value 0"]
127impl crate::Resettable for CHNL_REQ_MASK_SET_SPEC {
128    #[inline(always)]
129    fn reset_value() -> Self::Ux {
130        0
131    }
132}
eos_s3/sdma/chnl_req_mask_set.rs

eos_s3/sdma/
chnl_req_mask_set.rs
