eos_s3/sdma/
chnl_req_mask_clr.rs

1#[doc = "Register `CHNL_REQ_MASK_CLR` writer"]
2pub struct W(crate::W<CHNL_REQ_MASK_CLR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CHNL_REQ_MASK_CLR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CHNL_REQ_MASK_CLR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CHNL_REQ_MASK_CLR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `chnl_req_mask_cler` writer - Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req\\[C\\]
23and dma_sreq\\[C\\]. Write as: \n \n Bit \\[C\\]
24= 0 No effect. Use the chnl_req_mask_set Register to disable dma_req\\[C\\]
25and \n \n dma_sreq\\[C\\]
26from generating requests. \n \n Bit \\[C\\]
27= 1 Enables dma_req\\[C\\]
28or dma_sreq\\[C\\]
29to generate DMA requests. \n \n Writing to a bit where a DMA channel is not implemented has no effect."]
30pub struct CHNL_REQ_MASK_CLER_W<'a> {
31    w: &'a mut W,
32}
33impl<'a> CHNL_REQ_MASK_CLER_W<'a> {
34    #[doc = r"Writes raw bits to the field"]
35    #[inline(always)]
36    pub unsafe fn bits(self, value: u16) -> &'a mut W {
37        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
38        self.w
39    }
40}
41impl W {
42    #[doc = "Bits 0:15 - Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req\\[C\\]
43and dma_sreq\\[C\\]. Write as: \n \n Bit \\[C\\]
44= 0 No effect. Use the chnl_req_mask_set Register to disable dma_req\\[C\\]
45and \n \n dma_sreq\\[C\\]
46from generating requests. \n \n Bit \\[C\\]
47= 1 Enables dma_req\\[C\\]
48or dma_sreq\\[C\\]
49to generate DMA requests. \n \n Writing to a bit where a DMA channel is not implemented has no effect."]
50    #[inline(always)]
51    pub fn chnl_req_mask_cler(&mut self) -> CHNL_REQ_MASK_CLER_W {
52        CHNL_REQ_MASK_CLER_W { w: self }
53    }
54    #[doc = "Writes raw bits to the register."]
55    #[inline(always)]
56    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
57        self.0.bits(bits);
58        self
59    }
60}
61#[doc = "Set the appropriate bit to enable DMA requests for the channel corresponding to dma_req\\[C\\]
62and dma_sreq\\[C\\].\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_req_mask_clr](index.html) module"]
63pub struct CHNL_REQ_MASK_CLR_SPEC;
64impl crate::RegisterSpec for CHNL_REQ_MASK_CLR_SPEC {
65    type Ux = u32;
66}
67#[doc = "`write(|w| ..)` method takes [chnl_req_mask_clr::W](W) writer structure"]
68impl crate::Writable for CHNL_REQ_MASK_CLR_SPEC {
69    type Writer = W;
70}
71#[doc = "`reset()` method sets CHNL_REQ_MASK_CLR to value 0"]
72impl crate::Resettable for CHNL_REQ_MASK_CLR_SPEC {
73    #[inline(always)]
74    fn reset_value() -> Self::Ux {
75        0
76    }
77}
eos_s3/sdma/chnl_req_mask_clr.rs

eos_s3/sdma/
chnl_req_mask_clr.rs
