eos_s3/sdma/
chnl_pri_alt_clr.rs

1#[doc = "Register `CHNL_PRI_ALT_CLR` writer"]
2pub struct W(crate::W<CHNL_PRI_ALT_CLR_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<CHNL_PRI_ALT_CLR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<CHNL_PRI_ALT_CLR_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<CHNL_PRI_ALT_CLR_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `chnl_pri_alt_clr` writer - Set the appropriate bit to select the primary data structure for the corresponding DMA channel. Write as: \n \n Bit \\[C\\]
23= 0 No effect. Use the chnl_pri_alt_set Register to select the alternate data structure. \n \n Bit \\[C\\]
24= 1 Selects the primary data structure for channel C. \n \n Writing to a bit where a DMA channel is not implemented has no effect."]
25pub struct CHNL_PRI_ALT_CLR_W<'a> {
26    w: &'a mut W,
27}
28impl<'a> CHNL_PRI_ALT_CLR_W<'a> {
29    #[doc = r"Writes raw bits to the field"]
30    #[inline(always)]
31    pub unsafe fn bits(self, value: u16) -> &'a mut W {
32        self.w.bits = (self.w.bits & !0xffff) | (value as u32 & 0xffff);
33        self.w
34    }
35}
36impl W {
37    #[doc = "Bits 0:15 - Set the appropriate bit to select the primary data structure for the corresponding DMA channel. Write as: \n \n Bit \\[C\\]
38= 0 No effect. Use the chnl_pri_alt_set Register to select the alternate data structure. \n \n Bit \\[C\\]
39= 1 Selects the primary data structure for channel C. \n \n Writing to a bit where a DMA channel is not implemented has no effect."]
40    #[inline(always)]
41    pub fn chnl_pri_alt_clr(&mut self) -> CHNL_PRI_ALT_CLR_W {
42        CHNL_PRI_ALT_CLR_W { w: self }
43    }
44    #[doc = "Writes raw bits to the register."]
45    #[inline(always)]
46    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
47        self.0.bits(bits);
48        self
49    }
50}
51#[doc = "Set the appropriate bit to select the primary data structure for the corresponding DMA channel.\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [chnl_pri_alt_clr](index.html) module"]
52pub struct CHNL_PRI_ALT_CLR_SPEC;
53impl crate::RegisterSpec for CHNL_PRI_ALT_CLR_SPEC {
54    type Ux = u32;
55}
56#[doc = "`write(|w| ..)` method takes [chnl_pri_alt_clr::W](W) writer structure"]
57impl crate::Writable for CHNL_PRI_ALT_CLR_SPEC {
58    type Writer = W;
59}
60#[doc = "`reset()` method sets CHNL_PRI_ALT_CLR to value 0"]
61impl crate::Resettable for CHNL_PRI_ALT_CLR_SPEC {
62    #[inline(always)]
63    fn reset_value() -> Self::Ux {
64        0
65    }
66}
eos_s3/sdma/chnl_pri_alt_clr.rs

eos_s3/sdma/
chnl_pri_alt_clr.rs
