eos_s3/pmu/
pmu_timer_cfg_1.rs

1#[doc = "Register `PMU_TIMER_CFG_1` reader"]
2pub struct R(crate::R<PMU_TIMER_CFG_1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PMU_TIMER_CFG_1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PMU_TIMER_CFG_1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PMU_TIMER_CFG_1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PMU_TIMER_CFG_1` writer"]
17pub struct W(crate::W<PMU_TIMER_CFG_1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PMU_TIMER_CFG_1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PMU_TIMER_CFG_1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PMU_TIMER_CFG_1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PMU_Timer_Enable` reader - Set to enable PMU timer. Once disable, the PMU timer will be reset to all 0. FW need to disable the PMU timer once PMUT INT trigger. Please Note: It may take Up to 64uS to disable the time since this enable signal needs to sync to 32KHz clock domain from C10/C01 clock domain"]
38pub struct PMU_TIMER_ENABLE_R(crate::FieldReader<bool, bool>);
39impl PMU_TIMER_ENABLE_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: bool) -> Self {
42        PMU_TIMER_ENABLE_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for PMU_TIMER_ENABLE_R {
46    type Target = crate::FieldReader<bool, bool>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `PMU_Timer_Enable` writer - Set to enable PMU timer. Once disable, the PMU timer will be reset to all 0. FW need to disable the PMU timer once PMUT INT trigger. Please Note: It may take Up to 64uS to disable the time since this enable signal needs to sync to 32KHz clock domain from C10/C01 clock domain"]
53pub struct PMU_TIMER_ENABLE_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> PMU_TIMER_ENABLE_W<'a> {
57    #[doc = r"Sets the field bit"]
58    #[inline(always)]
59    pub fn set_bit(self) -> &'a mut W {
60        self.bit(true)
61    }
62    #[doc = r"Clears the field bit"]
63    #[inline(always)]
64    pub fn clear_bit(self) -> &'a mut W {
65        self.bit(false)
66    }
67    #[doc = r"Writes raw bits to the field"]
68    #[inline(always)]
69    pub fn bit(self, value: bool) -> &'a mut W {
70        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
71        self.w
72    }
73}
74impl R {
75    #[doc = "Bit 0 - Set to enable PMU timer. Once disable, the PMU timer will be reset to all 0. FW need to disable the PMU timer once PMUT INT trigger. Please Note: It may take Up to 64uS to disable the time since this enable signal needs to sync to 32KHz clock domain from C10/C01 clock domain"]
76    #[inline(always)]
77    pub fn pmu_timer_enable(&self) -> PMU_TIMER_ENABLE_R {
78        PMU_TIMER_ENABLE_R::new((self.bits & 0x01) != 0)
79    }
80}
81impl W {
82    #[doc = "Bit 0 - Set to enable PMU timer. Once disable, the PMU timer will be reset to all 0. FW need to disable the PMU timer once PMUT INT trigger. Please Note: It may take Up to 64uS to disable the time since this enable signal needs to sync to 32KHz clock domain from C10/C01 clock domain"]
83    #[inline(always)]
84    pub fn pmu_timer_enable(&mut self) -> PMU_TIMER_ENABLE_W {
85        PMU_TIMER_ENABLE_W { w: self }
86    }
87    #[doc = "Writes raw bits to the register."]
88    #[inline(always)]
89    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
90        self.0.bits(bits);
91        self
92    }
93}
94#[doc = "Control wether the PMU timer is enabled or disabled\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pmu_timer_cfg_1](index.html) module"]
95pub struct PMU_TIMER_CFG_1_SPEC;
96impl crate::RegisterSpec for PMU_TIMER_CFG_1_SPEC {
97    type Ux = u32;
98}
99#[doc = "`read()` method returns [pmu_timer_cfg_1::R](R) reader structure"]
100impl crate::Readable for PMU_TIMER_CFG_1_SPEC {
101    type Reader = R;
102}
103#[doc = "`write(|w| ..)` method takes [pmu_timer_cfg_1::W](W) writer structure"]
104impl crate::Writable for PMU_TIMER_CFG_1_SPEC {
105    type Writer = W;
106}
107#[doc = "`reset()` method sets PMU_TIMER_CFG_1 to value 0"]
108impl crate::Resettable for PMU_TIMER_CFG_1_SPEC {
109    #[inline(always)]
110    fn reset_value() -> Self::Ux {
111        0
112    }
113}
eos_s3/pmu/pmu_timer_cfg_1.rs

eos_s3/pmu/
pmu_timer_cfg_1.rs
