eos_s3/pmu/
mem_pwr_dwn_ctrl.rs

1#[doc = "Register `MEM_PWR_DWN_CTRL` reader"]
2pub struct R(crate::R<MEM_PWR_DWN_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<MEM_PWR_DWN_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<MEM_PWR_DWN_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<MEM_PWR_DWN_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `MEM_PWR_DWN_CTRL` writer"]
17pub struct W(crate::W<MEM_PWR_DWN_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<MEM_PWR_DWN_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<MEM_PWR_DWN_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<MEM_PWR_DWN_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S0` reader - Set to put M4S0 to Deep Sleep mode if M4 is in Shut Down Mode"]
38pub struct M4_SRAM_PD_CFG_0_M4S0_R(crate::FieldReader<bool, bool>);
39impl M4_SRAM_PD_CFG_0_M4S0_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: bool) -> Self {
42        M4_SRAM_PD_CFG_0_M4S0_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for M4_SRAM_PD_CFG_0_M4S0_R {
46    type Target = crate::FieldReader<bool, bool>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S0` writer - Set to put M4S0 to Deep Sleep mode if M4 is in Shut Down Mode"]
53pub struct M4_SRAM_PD_CFG_0_M4S0_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> M4_SRAM_PD_CFG_0_M4S0_W<'a> {
57    #[doc = r"Sets the field bit"]
58    #[inline(always)]
59    pub fn set_bit(self) -> &'a mut W {
60        self.bit(true)
61    }
62    #[doc = r"Clears the field bit"]
63    #[inline(always)]
64    pub fn clear_bit(self) -> &'a mut W {
65        self.bit(false)
66    }
67    #[doc = r"Writes raw bits to the field"]
68    #[inline(always)]
69    pub fn bit(self, value: bool) -> &'a mut W {
70        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
71        self.w
72    }
73}
74#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S1` reader - Set to put M4S1 to Deep Sleep mode if M4 is in Shut Down Mode"]
75pub struct M4_SRAM_PD_CFG_0_M4S1_R(crate::FieldReader<bool, bool>);
76impl M4_SRAM_PD_CFG_0_M4S1_R {
77    #[inline(always)]
78    pub(crate) fn new(bits: bool) -> Self {
79        M4_SRAM_PD_CFG_0_M4S1_R(crate::FieldReader::new(bits))
80    }
81}
82impl core::ops::Deref for M4_SRAM_PD_CFG_0_M4S1_R {
83    type Target = crate::FieldReader<bool, bool>;
84    #[inline(always)]
85    fn deref(&self) -> &Self::Target {
86        &self.0
87    }
88}
89#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S1` writer - Set to put M4S1 to Deep Sleep mode if M4 is in Shut Down Mode"]
90pub struct M4_SRAM_PD_CFG_0_M4S1_W<'a> {
91    w: &'a mut W,
92}
93impl<'a> M4_SRAM_PD_CFG_0_M4S1_W<'a> {
94    #[doc = r"Sets the field bit"]
95    #[inline(always)]
96    pub fn set_bit(self) -> &'a mut W {
97        self.bit(true)
98    }
99    #[doc = r"Clears the field bit"]
100    #[inline(always)]
101    pub fn clear_bit(self) -> &'a mut W {
102        self.bit(false)
103    }
104    #[doc = r"Writes raw bits to the field"]
105    #[inline(always)]
106    pub fn bit(self, value: bool) -> &'a mut W {
107        self.w.bits =
108            (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
109        self.w
110    }
111}
112#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S2` reader - Set to put M4S2 to Deep Sleep mode if M4 is in Shut Down Mode"]
113pub struct M4_SRAM_PD_CFG_0_M4S2_R(crate::FieldReader<bool, bool>);
114impl M4_SRAM_PD_CFG_0_M4S2_R {
115    #[inline(always)]
116    pub(crate) fn new(bits: bool) -> Self {
117        M4_SRAM_PD_CFG_0_M4S2_R(crate::FieldReader::new(bits))
118    }
119}
120impl core::ops::Deref for M4_SRAM_PD_CFG_0_M4S2_R {
121    type Target = crate::FieldReader<bool, bool>;
122    #[inline(always)]
123    fn deref(&self) -> &Self::Target {
124        &self.0
125    }
126}
127#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S2` writer - Set to put M4S2 to Deep Sleep mode if M4 is in Shut Down Mode"]
128pub struct M4_SRAM_PD_CFG_0_M4S2_W<'a> {
129    w: &'a mut W,
130}
131impl<'a> M4_SRAM_PD_CFG_0_M4S2_W<'a> {
132    #[doc = r"Sets the field bit"]
133    #[inline(always)]
134    pub fn set_bit(self) -> &'a mut W {
135        self.bit(true)
136    }
137    #[doc = r"Clears the field bit"]
138    #[inline(always)]
139    pub fn clear_bit(self) -> &'a mut W {
140        self.bit(false)
141    }
142    #[doc = r"Writes raw bits to the field"]
143    #[inline(always)]
144    pub fn bit(self, value: bool) -> &'a mut W {
145        self.w.bits =
146            (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
147        self.w
148    }
149}
150#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S3` reader - Set to put M4S3 to Deep Sleep mode if M4 is in Shut Down Mode"]
151pub struct M4_SRAM_PD_CFG_0_M4S3_R(crate::FieldReader<bool, bool>);
152impl M4_SRAM_PD_CFG_0_M4S3_R {
153    #[inline(always)]
154    pub(crate) fn new(bits: bool) -> Self {
155        M4_SRAM_PD_CFG_0_M4S3_R(crate::FieldReader::new(bits))
156    }
157}
158impl core::ops::Deref for M4_SRAM_PD_CFG_0_M4S3_R {
159    type Target = crate::FieldReader<bool, bool>;
160    #[inline(always)]
161    fn deref(&self) -> &Self::Target {
162        &self.0
163    }
164}
165#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S3` writer - Set to put M4S3 to Deep Sleep mode if M4 is in Shut Down Mode"]
166pub struct M4_SRAM_PD_CFG_0_M4S3_W<'a> {
167    w: &'a mut W,
168}
169impl<'a> M4_SRAM_PD_CFG_0_M4S3_W<'a> {
170    #[doc = r"Sets the field bit"]
171    #[inline(always)]
172    pub fn set_bit(self) -> &'a mut W {
173        self.bit(true)
174    }
175    #[doc = r"Clears the field bit"]
176    #[inline(always)]
177    pub fn clear_bit(self) -> &'a mut W {
178        self.bit(false)
179    }
180    #[doc = r"Writes raw bits to the field"]
181    #[inline(always)]
182    pub fn bit(self, value: bool) -> &'a mut W {
183        self.w.bits =
184            (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
185        self.w
186    }
187}
188#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S4` reader - Set to put M4S4 to Deep Sleep mode if M4 is in Shut Down Mode"]
189pub struct M4_SRAM_PD_CFG_0_M4S4_R(crate::FieldReader<bool, bool>);
190impl M4_SRAM_PD_CFG_0_M4S4_R {
191    #[inline(always)]
192    pub(crate) fn new(bits: bool) -> Self {
193        M4_SRAM_PD_CFG_0_M4S4_R(crate::FieldReader::new(bits))
194    }
195}
196impl core::ops::Deref for M4_SRAM_PD_CFG_0_M4S4_R {
197    type Target = crate::FieldReader<bool, bool>;
198    #[inline(always)]
199    fn deref(&self) -> &Self::Target {
200        &self.0
201    }
202}
203#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S4` writer - Set to put M4S4 to Deep Sleep mode if M4 is in Shut Down Mode"]
204pub struct M4_SRAM_PD_CFG_0_M4S4_W<'a> {
205    w: &'a mut W,
206}
207impl<'a> M4_SRAM_PD_CFG_0_M4S4_W<'a> {
208    #[doc = r"Sets the field bit"]
209    #[inline(always)]
210    pub fn set_bit(self) -> &'a mut W {
211        self.bit(true)
212    }
213    #[doc = r"Clears the field bit"]
214    #[inline(always)]
215    pub fn clear_bit(self) -> &'a mut W {
216        self.bit(false)
217    }
218    #[doc = r"Writes raw bits to the field"]
219    #[inline(always)]
220    pub fn bit(self, value: bool) -> &'a mut W {
221        self.w.bits =
222            (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
223        self.w
224    }
225}
226#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S5` reader - Set to put M4S5 to Deep Sleep mode if M4 is in Shut Down Mode"]
227pub struct M4_SRAM_PD_CFG_0_M4S5_R(crate::FieldReader<bool, bool>);
228impl M4_SRAM_PD_CFG_0_M4S5_R {
229    #[inline(always)]
230    pub(crate) fn new(bits: bool) -> Self {
231        M4_SRAM_PD_CFG_0_M4S5_R(crate::FieldReader::new(bits))
232    }
233}
234impl core::ops::Deref for M4_SRAM_PD_CFG_0_M4S5_R {
235    type Target = crate::FieldReader<bool, bool>;
236    #[inline(always)]
237    fn deref(&self) -> &Self::Target {
238        &self.0
239    }
240}
241#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S5` writer - Set to put M4S5 to Deep Sleep mode if M4 is in Shut Down Mode"]
242pub struct M4_SRAM_PD_CFG_0_M4S5_W<'a> {
243    w: &'a mut W,
244}
245impl<'a> M4_SRAM_PD_CFG_0_M4S5_W<'a> {
246    #[doc = r"Sets the field bit"]
247    #[inline(always)]
248    pub fn set_bit(self) -> &'a mut W {
249        self.bit(true)
250    }
251    #[doc = r"Clears the field bit"]
252    #[inline(always)]
253    pub fn clear_bit(self) -> &'a mut W {
254        self.bit(false)
255    }
256    #[doc = r"Writes raw bits to the field"]
257    #[inline(always)]
258    pub fn bit(self, value: bool) -> &'a mut W {
259        self.w.bits =
260            (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
261        self.w
262    }
263}
264#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S6` reader - Set to put M4S6 to Deep Sleep mode if M4 is in Shut Down Mode"]
265pub struct M4_SRAM_PD_CFG_0_M4S6_R(crate::FieldReader<bool, bool>);
266impl M4_SRAM_PD_CFG_0_M4S6_R {
267    #[inline(always)]
268    pub(crate) fn new(bits: bool) -> Self {
269        M4_SRAM_PD_CFG_0_M4S6_R(crate::FieldReader::new(bits))
270    }
271}
272impl core::ops::Deref for M4_SRAM_PD_CFG_0_M4S6_R {
273    type Target = crate::FieldReader<bool, bool>;
274    #[inline(always)]
275    fn deref(&self) -> &Self::Target {
276        &self.0
277    }
278}
279#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S6` writer - Set to put M4S6 to Deep Sleep mode if M4 is in Shut Down Mode"]
280pub struct M4_SRAM_PD_CFG_0_M4S6_W<'a> {
281    w: &'a mut W,
282}
283impl<'a> M4_SRAM_PD_CFG_0_M4S6_W<'a> {
284    #[doc = r"Sets the field bit"]
285    #[inline(always)]
286    pub fn set_bit(self) -> &'a mut W {
287        self.bit(true)
288    }
289    #[doc = r"Clears the field bit"]
290    #[inline(always)]
291    pub fn clear_bit(self) -> &'a mut W {
292        self.bit(false)
293    }
294    #[doc = r"Writes raw bits to the field"]
295    #[inline(always)]
296    pub fn bit(self, value: bool) -> &'a mut W {
297        self.w.bits =
298            (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
299        self.w
300    }
301}
302#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S7` reader - Set to put M4S7 to Deep Sleep mode if M4 is in Shut Down Mode"]
303pub struct M4_SRAM_PD_CFG_0_M4S7_R(crate::FieldReader<bool, bool>);
304impl M4_SRAM_PD_CFG_0_M4S7_R {
305    #[inline(always)]
306    pub(crate) fn new(bits: bool) -> Self {
307        M4_SRAM_PD_CFG_0_M4S7_R(crate::FieldReader::new(bits))
308    }
309}
310impl core::ops::Deref for M4_SRAM_PD_CFG_0_M4S7_R {
311    type Target = crate::FieldReader<bool, bool>;
312    #[inline(always)]
313    fn deref(&self) -> &Self::Target {
314        &self.0
315    }
316}
317#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S7` writer - Set to put M4S7 to Deep Sleep mode if M4 is in Shut Down Mode"]
318pub struct M4_SRAM_PD_CFG_0_M4S7_W<'a> {
319    w: &'a mut W,
320}
321impl<'a> M4_SRAM_PD_CFG_0_M4S7_W<'a> {
322    #[doc = r"Sets the field bit"]
323    #[inline(always)]
324    pub fn set_bit(self) -> &'a mut W {
325        self.bit(true)
326    }
327    #[doc = r"Clears the field bit"]
328    #[inline(always)]
329    pub fn clear_bit(self) -> &'a mut W {
330        self.bit(false)
331    }
332    #[doc = r"Writes raw bits to the field"]
333    #[inline(always)]
334    pub fn bit(self, value: bool) -> &'a mut W {
335        self.w.bits =
336            (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
337        self.w
338    }
339}
340#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S8` reader - Set to put M4S8 to Deep Sleep mode if M4 is in Shut Down Mode"]
341pub struct M4_SRAM_PD_CFG_0_M4S8_R(crate::FieldReader<bool, bool>);
342impl M4_SRAM_PD_CFG_0_M4S8_R {
343    #[inline(always)]
344    pub(crate) fn new(bits: bool) -> Self {
345        M4_SRAM_PD_CFG_0_M4S8_R(crate::FieldReader::new(bits))
346    }
347}
348impl core::ops::Deref for M4_SRAM_PD_CFG_0_M4S8_R {
349    type Target = crate::FieldReader<bool, bool>;
350    #[inline(always)]
351    fn deref(&self) -> &Self::Target {
352        &self.0
353    }
354}
355#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S8` writer - Set to put M4S8 to Deep Sleep mode if M4 is in Shut Down Mode"]
356pub struct M4_SRAM_PD_CFG_0_M4S8_W<'a> {
357    w: &'a mut W,
358}
359impl<'a> M4_SRAM_PD_CFG_0_M4S8_W<'a> {
360    #[doc = r"Sets the field bit"]
361    #[inline(always)]
362    pub fn set_bit(self) -> &'a mut W {
363        self.bit(true)
364    }
365    #[doc = r"Clears the field bit"]
366    #[inline(always)]
367    pub fn clear_bit(self) -> &'a mut W {
368        self.bit(false)
369    }
370    #[doc = r"Writes raw bits to the field"]
371    #[inline(always)]
372    pub fn bit(self, value: bool) -> &'a mut W {
373        self.w.bits =
374            (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
375        self.w
376    }
377}
378#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S9` reader - Set to put M4S9 to Deep Sleep mode if M4 is in Shut Down Mode"]
379pub struct M4_SRAM_PD_CFG_0_M4S9_R(crate::FieldReader<bool, bool>);
380impl M4_SRAM_PD_CFG_0_M4S9_R {
381    #[inline(always)]
382    pub(crate) fn new(bits: bool) -> Self {
383        M4_SRAM_PD_CFG_0_M4S9_R(crate::FieldReader::new(bits))
384    }
385}
386impl core::ops::Deref for M4_SRAM_PD_CFG_0_M4S9_R {
387    type Target = crate::FieldReader<bool, bool>;
388    #[inline(always)]
389    fn deref(&self) -> &Self::Target {
390        &self.0
391    }
392}
393#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S9` writer - Set to put M4S9 to Deep Sleep mode if M4 is in Shut Down Mode"]
394pub struct M4_SRAM_PD_CFG_0_M4S9_W<'a> {
395    w: &'a mut W,
396}
397impl<'a> M4_SRAM_PD_CFG_0_M4S9_W<'a> {
398    #[doc = r"Sets the field bit"]
399    #[inline(always)]
400    pub fn set_bit(self) -> &'a mut W {
401        self.bit(true)
402    }
403    #[doc = r"Clears the field bit"]
404    #[inline(always)]
405    pub fn clear_bit(self) -> &'a mut W {
406        self.bit(false)
407    }
408    #[doc = r"Writes raw bits to the field"]
409    #[inline(always)]
410    pub fn bit(self, value: bool) -> &'a mut W {
411        self.w.bits =
412            (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
413        self.w
414    }
415}
416#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S10` reader - Set tout M4S10 to Deep Sleep mode if M4 is in Shut Down Mode"]
417pub struct M4_SRAM_PD_CFG_0_M4S10_R(crate::FieldReader<bool, bool>);
418impl M4_SRAM_PD_CFG_0_M4S10_R {
419    #[inline(always)]
420    pub(crate) fn new(bits: bool) -> Self {
421        M4_SRAM_PD_CFG_0_M4S10_R(crate::FieldReader::new(bits))
422    }
423}
424impl core::ops::Deref for M4_SRAM_PD_CFG_0_M4S10_R {
425    type Target = crate::FieldReader<bool, bool>;
426    #[inline(always)]
427    fn deref(&self) -> &Self::Target {
428        &self.0
429    }
430}
431#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S10` writer - Set tout M4S10 to Deep Sleep mode if M4 is in Shut Down Mode"]
432pub struct M4_SRAM_PD_CFG_0_M4S10_W<'a> {
433    w: &'a mut W,
434}
435impl<'a> M4_SRAM_PD_CFG_0_M4S10_W<'a> {
436    #[doc = r"Sets the field bit"]
437    #[inline(always)]
438    pub fn set_bit(self) -> &'a mut W {
439        self.bit(true)
440    }
441    #[doc = r"Clears the field bit"]
442    #[inline(always)]
443    pub fn clear_bit(self) -> &'a mut W {
444        self.bit(false)
445    }
446    #[doc = r"Writes raw bits to the field"]
447    #[inline(always)]
448    pub fn bit(self, value: bool) -> &'a mut W {
449        self.w.bits =
450            (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
451        self.w
452    }
453}
454#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S11` reader - Set to put M4S11 to Deep Sleep mode if M4 is in Shut Down Mode"]
455pub struct M4_SRAM_PD_CFG_0_M4S11_R(crate::FieldReader<bool, bool>);
456impl M4_SRAM_PD_CFG_0_M4S11_R {
457    #[inline(always)]
458    pub(crate) fn new(bits: bool) -> Self {
459        M4_SRAM_PD_CFG_0_M4S11_R(crate::FieldReader::new(bits))
460    }
461}
462impl core::ops::Deref for M4_SRAM_PD_CFG_0_M4S11_R {
463    type Target = crate::FieldReader<bool, bool>;
464    #[inline(always)]
465    fn deref(&self) -> &Self::Target {
466        &self.0
467    }
468}
469#[doc = "Field `M4_SRAM_PD_Cfg_0_M4S11` writer - Set to put M4S11 to Deep Sleep mode if M4 is in Shut Down Mode"]
470pub struct M4_SRAM_PD_CFG_0_M4S11_W<'a> {
471    w: &'a mut W,
472}
473impl<'a> M4_SRAM_PD_CFG_0_M4S11_W<'a> {
474    #[doc = r"Sets the field bit"]
475    #[inline(always)]
476    pub fn set_bit(self) -> &'a mut W {
477        self.bit(true)
478    }
479    #[doc = r"Clears the field bit"]
480    #[inline(always)]
481    pub fn clear_bit(self) -> &'a mut W {
482        self.bit(false)
483    }
484    #[doc = r"Writes raw bits to the field"]
485    #[inline(always)]
486    pub fn bit(self, value: bool) -> &'a mut W {
487        self.w.bits =
488            (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
489        self.w
490    }
491}
492#[doc = "Field `M4_SRAM_PD_Cfg_1_M4S12` reader - Set to put M4S12 to Deep Sleep mode if M4 is in Shut Down Mode"]
493pub struct M4_SRAM_PD_CFG_1_M4S12_R(crate::FieldReader<bool, bool>);
494impl M4_SRAM_PD_CFG_1_M4S12_R {
495    #[inline(always)]
496    pub(crate) fn new(bits: bool) -> Self {
497        M4_SRAM_PD_CFG_1_M4S12_R(crate::FieldReader::new(bits))
498    }
499}
500impl core::ops::Deref for M4_SRAM_PD_CFG_1_M4S12_R {
501    type Target = crate::FieldReader<bool, bool>;
502    #[inline(always)]
503    fn deref(&self) -> &Self::Target {
504        &self.0
505    }
506}
507#[doc = "Field `M4_SRAM_PD_Cfg_1_M4S13` reader - Set to put M4S13 to Deep Sleep mode if M4 is in Shut Down Mode"]
508pub struct M4_SRAM_PD_CFG_1_M4S13_R(crate::FieldReader<bool, bool>);
509impl M4_SRAM_PD_CFG_1_M4S13_R {
510    #[inline(always)]
511    pub(crate) fn new(bits: bool) -> Self {
512        M4_SRAM_PD_CFG_1_M4S13_R(crate::FieldReader::new(bits))
513    }
514}
515impl core::ops::Deref for M4_SRAM_PD_CFG_1_M4S13_R {
516    type Target = crate::FieldReader<bool, bool>;
517    #[inline(always)]
518    fn deref(&self) -> &Self::Target {
519        &self.0
520    }
521}
522#[doc = "Field `M4_SRAM_PD_Cfg_1_M4S14` reader - Set to put M4S14 to Deep Sleep mode if M4 is in Shut Down Mode"]
523pub struct M4_SRAM_PD_CFG_1_M4S14_R(crate::FieldReader<bool, bool>);
524impl M4_SRAM_PD_CFG_1_M4S14_R {
525    #[inline(always)]
526    pub(crate) fn new(bits: bool) -> Self {
527        M4_SRAM_PD_CFG_1_M4S14_R(crate::FieldReader::new(bits))
528    }
529}
530impl core::ops::Deref for M4_SRAM_PD_CFG_1_M4S14_R {
531    type Target = crate::FieldReader<bool, bool>;
532    #[inline(always)]
533    fn deref(&self) -> &Self::Target {
534        &self.0
535    }
536}
537#[doc = "Field `M4_SRAM_PD_Cfg_1_M4S15` reader - Set to put M4S15 to Deep Sleep mode if M4 is in Shut Down Mode"]
538pub struct M4_SRAM_PD_CFG_1_M4S15_R(crate::FieldReader<bool, bool>);
539impl M4_SRAM_PD_CFG_1_M4S15_R {
540    #[inline(always)]
541    pub(crate) fn new(bits: bool) -> Self {
542        M4_SRAM_PD_CFG_1_M4S15_R(crate::FieldReader::new(bits))
543    }
544}
545impl core::ops::Deref for M4_SRAM_PD_CFG_1_M4S15_R {
546    type Target = crate::FieldReader<bool, bool>;
547    #[inline(always)]
548    fn deref(&self) -> &Self::Target {
549        &self.0
550    }
551}
552#[doc = "Field `FFE_SRAM_PD_Cfg` reader - Set to assert the DS pin of the SRAM Macro inside FFE power domain if FFE power domain is in Deep Sleep"]
553pub struct FFE_SRAM_PD_CFG_R(crate::FieldReader<bool, bool>);
554impl FFE_SRAM_PD_CFG_R {
555    #[inline(always)]
556    pub(crate) fn new(bits: bool) -> Self {
557        FFE_SRAM_PD_CFG_R(crate::FieldReader::new(bits))
558    }
559}
560impl core::ops::Deref for FFE_SRAM_PD_CFG_R {
561    type Target = crate::FieldReader<bool, bool>;
562    #[inline(always)]
563    fn deref(&self) -> &Self::Target {
564        &self.0
565    }
566}
567#[doc = "Field `FFE_SRAM_PD_Cfg` writer - Set to assert the DS pin of the SRAM Macro inside FFE power domain if FFE power domain is in Deep Sleep"]
568pub struct FFE_SRAM_PD_CFG_W<'a> {
569    w: &'a mut W,
570}
571impl<'a> FFE_SRAM_PD_CFG_W<'a> {
572    #[doc = r"Sets the field bit"]
573    #[inline(always)]
574    pub fn set_bit(self) -> &'a mut W {
575        self.bit(true)
576    }
577    #[doc = r"Clears the field bit"]
578    #[inline(always)]
579    pub fn clear_bit(self) -> &'a mut W {
580        self.bit(false)
581    }
582    #[doc = r"Writes raw bits to the field"]
583    #[inline(always)]
584    pub fn bit(self, value: bool) -> &'a mut W {
585        self.w.bits =
586            (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
587        self.w
588    }
589}
590#[doc = "Field `PF_SRAM_PD_Cfg` reader - Set to assert the DS pin of the SRAM Macro inside PF power domain if PF power domain is in Deep Sleep"]
591pub struct PF_SRAM_PD_CFG_R(crate::FieldReader<bool, bool>);
592impl PF_SRAM_PD_CFG_R {
593    #[inline(always)]
594    pub(crate) fn new(bits: bool) -> Self {
595        PF_SRAM_PD_CFG_R(crate::FieldReader::new(bits))
596    }
597}
598impl core::ops::Deref for PF_SRAM_PD_CFG_R {
599    type Target = crate::FieldReader<bool, bool>;
600    #[inline(always)]
601    fn deref(&self) -> &Self::Target {
602        &self.0
603    }
604}
605#[doc = "Field `PF_SRAM_PD_Cfg` writer - Set to assert the DS pin of the SRAM Macro inside PF power domain if PF power domain is in Deep Sleep"]
606pub struct PF_SRAM_PD_CFG_W<'a> {
607    w: &'a mut W,
608}
609impl<'a> PF_SRAM_PD_CFG_W<'a> {
610    #[doc = r"Sets the field bit"]
611    #[inline(always)]
612    pub fn set_bit(self) -> &'a mut W {
613        self.bit(true)
614    }
615    #[doc = r"Clears the field bit"]
616    #[inline(always)]
617    pub fn clear_bit(self) -> &'a mut W {
618        self.bit(false)
619    }
620    #[doc = r"Writes raw bits to the field"]
621    #[inline(always)]
622    pub fn bit(self, value: bool) -> &'a mut W {
623        self.w.bits =
624            (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
625        self.w
626    }
627}
628#[doc = "Field `SDMA_SRAM_PD_Cfg` reader - Set to assert the DS pin of the SRAM Macro inside SDMA power domain if SDMA power domain is in Deep Sleep or Shut Down Mode."]
629pub struct SDMA_SRAM_PD_CFG_R(crate::FieldReader<bool, bool>);
630impl SDMA_SRAM_PD_CFG_R {
631    #[inline(always)]
632    pub(crate) fn new(bits: bool) -> Self {
633        SDMA_SRAM_PD_CFG_R(crate::FieldReader::new(bits))
634    }
635}
636impl core::ops::Deref for SDMA_SRAM_PD_CFG_R {
637    type Target = crate::FieldReader<bool, bool>;
638    #[inline(always)]
639    fn deref(&self) -> &Self::Target {
640        &self.0
641    }
642}
643#[doc = "Field `SDMA_SRAM_PD_Cfg` writer - Set to assert the DS pin of the SRAM Macro inside SDMA power domain if SDMA power domain is in Deep Sleep or Shut Down Mode."]
644pub struct SDMA_SRAM_PD_CFG_W<'a> {
645    w: &'a mut W,
646}
647impl<'a> SDMA_SRAM_PD_CFG_W<'a> {
648    #[doc = r"Sets the field bit"]
649    #[inline(always)]
650    pub fn set_bit(self) -> &'a mut W {
651        self.bit(true)
652    }
653    #[doc = r"Clears the field bit"]
654    #[inline(always)]
655    pub fn clear_bit(self) -> &'a mut W {
656        self.bit(false)
657    }
658    #[doc = r"Writes raw bits to the field"]
659    #[inline(always)]
660    pub fn bit(self, value: bool) -> &'a mut W {
661        self.w.bits =
662            (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
663        self.w
664    }
665}
666impl R {
667    #[doc = "Bit 0 - Set to put M4S0 to Deep Sleep mode if M4 is in Shut Down Mode"]
668    #[inline(always)]
669    pub fn m4_sram_pd_cfg_0_m4s0(&self) -> M4_SRAM_PD_CFG_0_M4S0_R {
670        M4_SRAM_PD_CFG_0_M4S0_R::new((self.bits & 0x01) != 0)
671    }
672    #[doc = "Bit 1 - Set to put M4S1 to Deep Sleep mode if M4 is in Shut Down Mode"]
673    #[inline(always)]
674    pub fn m4_sram_pd_cfg_0_m4s1(&self) -> M4_SRAM_PD_CFG_0_M4S1_R {
675        M4_SRAM_PD_CFG_0_M4S1_R::new(((self.bits >> 1) & 0x01) != 0)
676    }
677    #[doc = "Bit 2 - Set to put M4S2 to Deep Sleep mode if M4 is in Shut Down Mode"]
678    #[inline(always)]
679    pub fn m4_sram_pd_cfg_0_m4s2(&self) -> M4_SRAM_PD_CFG_0_M4S2_R {
680        M4_SRAM_PD_CFG_0_M4S2_R::new(((self.bits >> 2) & 0x01) != 0)
681    }
682    #[doc = "Bit 3 - Set to put M4S3 to Deep Sleep mode if M4 is in Shut Down Mode"]
683    #[inline(always)]
684    pub fn m4_sram_pd_cfg_0_m4s3(&self) -> M4_SRAM_PD_CFG_0_M4S3_R {
685        M4_SRAM_PD_CFG_0_M4S3_R::new(((self.bits >> 3) & 0x01) != 0)
686    }
687    #[doc = "Bit 4 - Set to put M4S4 to Deep Sleep mode if M4 is in Shut Down Mode"]
688    #[inline(always)]
689    pub fn m4_sram_pd_cfg_0_m4s4(&self) -> M4_SRAM_PD_CFG_0_M4S4_R {
690        M4_SRAM_PD_CFG_0_M4S4_R::new(((self.bits >> 4) & 0x01) != 0)
691    }
692    #[doc = "Bit 5 - Set to put M4S5 to Deep Sleep mode if M4 is in Shut Down Mode"]
693    #[inline(always)]
694    pub fn m4_sram_pd_cfg_0_m4s5(&self) -> M4_SRAM_PD_CFG_0_M4S5_R {
695        M4_SRAM_PD_CFG_0_M4S5_R::new(((self.bits >> 5) & 0x01) != 0)
696    }
697    #[doc = "Bit 6 - Set to put M4S6 to Deep Sleep mode if M4 is in Shut Down Mode"]
698    #[inline(always)]
699    pub fn m4_sram_pd_cfg_0_m4s6(&self) -> M4_SRAM_PD_CFG_0_M4S6_R {
700        M4_SRAM_PD_CFG_0_M4S6_R::new(((self.bits >> 6) & 0x01) != 0)
701    }
702    #[doc = "Bit 7 - Set to put M4S7 to Deep Sleep mode if M4 is in Shut Down Mode"]
703    #[inline(always)]
704    pub fn m4_sram_pd_cfg_0_m4s7(&self) -> M4_SRAM_PD_CFG_0_M4S7_R {
705        M4_SRAM_PD_CFG_0_M4S7_R::new(((self.bits >> 7) & 0x01) != 0)
706    }
707    #[doc = "Bit 8 - Set to put M4S8 to Deep Sleep mode if M4 is in Shut Down Mode"]
708    #[inline(always)]
709    pub fn m4_sram_pd_cfg_0_m4s8(&self) -> M4_SRAM_PD_CFG_0_M4S8_R {
710        M4_SRAM_PD_CFG_0_M4S8_R::new(((self.bits >> 8) & 0x01) != 0)
711    }
712    #[doc = "Bit 9 - Set to put M4S9 to Deep Sleep mode if M4 is in Shut Down Mode"]
713    #[inline(always)]
714    pub fn m4_sram_pd_cfg_0_m4s9(&self) -> M4_SRAM_PD_CFG_0_M4S9_R {
715        M4_SRAM_PD_CFG_0_M4S9_R::new(((self.bits >> 9) & 0x01) != 0)
716    }
717    #[doc = "Bit 10 - Set tout M4S10 to Deep Sleep mode if M4 is in Shut Down Mode"]
718    #[inline(always)]
719    pub fn m4_sram_pd_cfg_0_m4s10(&self) -> M4_SRAM_PD_CFG_0_M4S10_R {
720        M4_SRAM_PD_CFG_0_M4S10_R::new(((self.bits >> 10) & 0x01) != 0)
721    }
722    #[doc = "Bit 11 - Set to put M4S11 to Deep Sleep mode if M4 is in Shut Down Mode"]
723    #[inline(always)]
724    pub fn m4_sram_pd_cfg_0_m4s11(&self) -> M4_SRAM_PD_CFG_0_M4S11_R {
725        M4_SRAM_PD_CFG_0_M4S11_R::new(((self.bits >> 11) & 0x01) != 0)
726    }
727    #[doc = "Bit 12 - Set to put M4S12 to Deep Sleep mode if M4 is in Shut Down Mode"]
728    #[inline(always)]
729    pub fn m4_sram_pd_cfg_1_m4s12(&self) -> M4_SRAM_PD_CFG_1_M4S12_R {
730        M4_SRAM_PD_CFG_1_M4S12_R::new(((self.bits >> 12) & 0x01) != 0)
731    }
732    #[doc = "Bit 13 - Set to put M4S13 to Deep Sleep mode if M4 is in Shut Down Mode"]
733    #[inline(always)]
734    pub fn m4_sram_pd_cfg_1_m4s13(&self) -> M4_SRAM_PD_CFG_1_M4S13_R {
735        M4_SRAM_PD_CFG_1_M4S13_R::new(((self.bits >> 13) & 0x01) != 0)
736    }
737    #[doc = "Bit 14 - Set to put M4S14 to Deep Sleep mode if M4 is in Shut Down Mode"]
738    #[inline(always)]
739    pub fn m4_sram_pd_cfg_1_m4s14(&self) -> M4_SRAM_PD_CFG_1_M4S14_R {
740        M4_SRAM_PD_CFG_1_M4S14_R::new(((self.bits >> 14) & 0x01) != 0)
741    }
742    #[doc = "Bit 15 - Set to put M4S15 to Deep Sleep mode if M4 is in Shut Down Mode"]
743    #[inline(always)]
744    pub fn m4_sram_pd_cfg_1_m4s15(&self) -> M4_SRAM_PD_CFG_1_M4S15_R {
745        M4_SRAM_PD_CFG_1_M4S15_R::new(((self.bits >> 15) & 0x01) != 0)
746    }
747    #[doc = "Bit 16 - Set to assert the DS pin of the SRAM Macro inside FFE power domain if FFE power domain is in Deep Sleep"]
748    #[inline(always)]
749    pub fn ffe_sram_pd_cfg(&self) -> FFE_SRAM_PD_CFG_R {
750        FFE_SRAM_PD_CFG_R::new(((self.bits >> 16) & 0x01) != 0)
751    }
752    #[doc = "Bit 17 - Set to assert the DS pin of the SRAM Macro inside PF power domain if PF power domain is in Deep Sleep"]
753    #[inline(always)]
754    pub fn pf_sram_pd_cfg(&self) -> PF_SRAM_PD_CFG_R {
755        PF_SRAM_PD_CFG_R::new(((self.bits >> 17) & 0x01) != 0)
756    }
757    #[doc = "Bit 18 - Set to assert the DS pin of the SRAM Macro inside SDMA power domain if SDMA power domain is in Deep Sleep or Shut Down Mode."]
758    #[inline(always)]
759    pub fn sdma_sram_pd_cfg(&self) -> SDMA_SRAM_PD_CFG_R {
760        SDMA_SRAM_PD_CFG_R::new(((self.bits >> 18) & 0x01) != 0)
761    }
762}
763impl W {
764    #[doc = "Bit 0 - Set to put M4S0 to Deep Sleep mode if M4 is in Shut Down Mode"]
765    #[inline(always)]
766    pub fn m4_sram_pd_cfg_0_m4s0(&mut self) -> M4_SRAM_PD_CFG_0_M4S0_W {
767        M4_SRAM_PD_CFG_0_M4S0_W { w: self }
768    }
769    #[doc = "Bit 1 - Set to put M4S1 to Deep Sleep mode if M4 is in Shut Down Mode"]
770    #[inline(always)]
771    pub fn m4_sram_pd_cfg_0_m4s1(&mut self) -> M4_SRAM_PD_CFG_0_M4S1_W {
772        M4_SRAM_PD_CFG_0_M4S1_W { w: self }
773    }
774    #[doc = "Bit 2 - Set to put M4S2 to Deep Sleep mode if M4 is in Shut Down Mode"]
775    #[inline(always)]
776    pub fn m4_sram_pd_cfg_0_m4s2(&mut self) -> M4_SRAM_PD_CFG_0_M4S2_W {
777        M4_SRAM_PD_CFG_0_M4S2_W { w: self }
778    }
779    #[doc = "Bit 3 - Set to put M4S3 to Deep Sleep mode if M4 is in Shut Down Mode"]
780    #[inline(always)]
781    pub fn m4_sram_pd_cfg_0_m4s3(&mut self) -> M4_SRAM_PD_CFG_0_M4S3_W {
782        M4_SRAM_PD_CFG_0_M4S3_W { w: self }
783    }
784    #[doc = "Bit 4 - Set to put M4S4 to Deep Sleep mode if M4 is in Shut Down Mode"]
785    #[inline(always)]
786    pub fn m4_sram_pd_cfg_0_m4s4(&mut self) -> M4_SRAM_PD_CFG_0_M4S4_W {
787        M4_SRAM_PD_CFG_0_M4S4_W { w: self }
788    }
789    #[doc = "Bit 5 - Set to put M4S5 to Deep Sleep mode if M4 is in Shut Down Mode"]
790    #[inline(always)]
791    pub fn m4_sram_pd_cfg_0_m4s5(&mut self) -> M4_SRAM_PD_CFG_0_M4S5_W {
792        M4_SRAM_PD_CFG_0_M4S5_W { w: self }
793    }
794    #[doc = "Bit 6 - Set to put M4S6 to Deep Sleep mode if M4 is in Shut Down Mode"]
795    #[inline(always)]
796    pub fn m4_sram_pd_cfg_0_m4s6(&mut self) -> M4_SRAM_PD_CFG_0_M4S6_W {
797        M4_SRAM_PD_CFG_0_M4S6_W { w: self }
798    }
799    #[doc = "Bit 7 - Set to put M4S7 to Deep Sleep mode if M4 is in Shut Down Mode"]
800    #[inline(always)]
801    pub fn m4_sram_pd_cfg_0_m4s7(&mut self) -> M4_SRAM_PD_CFG_0_M4S7_W {
802        M4_SRAM_PD_CFG_0_M4S7_W { w: self }
803    }
804    #[doc = "Bit 8 - Set to put M4S8 to Deep Sleep mode if M4 is in Shut Down Mode"]
805    #[inline(always)]
806    pub fn m4_sram_pd_cfg_0_m4s8(&mut self) -> M4_SRAM_PD_CFG_0_M4S8_W {
807        M4_SRAM_PD_CFG_0_M4S8_W { w: self }
808    }
809    #[doc = "Bit 9 - Set to put M4S9 to Deep Sleep mode if M4 is in Shut Down Mode"]
810    #[inline(always)]
811    pub fn m4_sram_pd_cfg_0_m4s9(&mut self) -> M4_SRAM_PD_CFG_0_M4S9_W {
812        M4_SRAM_PD_CFG_0_M4S9_W { w: self }
813    }
814    #[doc = "Bit 10 - Set tout M4S10 to Deep Sleep mode if M4 is in Shut Down Mode"]
815    #[inline(always)]
816    pub fn m4_sram_pd_cfg_0_m4s10(&mut self) -> M4_SRAM_PD_CFG_0_M4S10_W {
817        M4_SRAM_PD_CFG_0_M4S10_W { w: self }
818    }
819    #[doc = "Bit 11 - Set to put M4S11 to Deep Sleep mode if M4 is in Shut Down Mode"]
820    #[inline(always)]
821    pub fn m4_sram_pd_cfg_0_m4s11(&mut self) -> M4_SRAM_PD_CFG_0_M4S11_W {
822        M4_SRAM_PD_CFG_0_M4S11_W { w: self }
823    }
824    #[doc = "Bit 16 - Set to assert the DS pin of the SRAM Macro inside FFE power domain if FFE power domain is in Deep Sleep"]
825    #[inline(always)]
826    pub fn ffe_sram_pd_cfg(&mut self) -> FFE_SRAM_PD_CFG_W {
827        FFE_SRAM_PD_CFG_W { w: self }
828    }
829    #[doc = "Bit 17 - Set to assert the DS pin of the SRAM Macro inside PF power domain if PF power domain is in Deep Sleep"]
830    #[inline(always)]
831    pub fn pf_sram_pd_cfg(&mut self) -> PF_SRAM_PD_CFG_W {
832        PF_SRAM_PD_CFG_W { w: self }
833    }
834    #[doc = "Bit 18 - Set to assert the DS pin of the SRAM Macro inside SDMA power domain if SDMA power domain is in Deep Sleep or Shut Down Mode."]
835    #[inline(always)]
836    pub fn sdma_sram_pd_cfg(&mut self) -> SDMA_SRAM_PD_CFG_W {
837        SDMA_SRAM_PD_CFG_W { w: self }
838    }
839    #[doc = "Writes raw bits to the register."]
840    #[inline(always)]
841    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
842        self.0.bits(bits);
843        self
844    }
845}
846#[doc = "Memory Power Down Control\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mem_pwr_dwn_ctrl](index.html) module"]
847pub struct MEM_PWR_DWN_CTRL_SPEC;
848impl crate::RegisterSpec for MEM_PWR_DWN_CTRL_SPEC {
849    type Ux = u32;
850}
851#[doc = "`read()` method returns [mem_pwr_dwn_ctrl::R](R) reader structure"]
852impl crate::Readable for MEM_PWR_DWN_CTRL_SPEC {
853    type Reader = R;
854}
855#[doc = "`write(|w| ..)` method takes [mem_pwr_dwn_ctrl::W](W) writer structure"]
856impl crate::Writable for MEM_PWR_DWN_CTRL_SPEC {
857    type Writer = W;
858}
859#[doc = "`reset()` method sets MEM_PWR_DWN_CTRL to value 0"]
860impl crate::Resettable for MEM_PWR_DWN_CTRL_SPEC {
861    #[inline(always)]
862    fn reset_value() -> Self::Ux {
863        0
864    }
865}
eos_s3/pmu/mem_pwr_dwn_ctrl.rs

eos_s3/pmu/
mem_pwr_dwn_ctrl.rs
