eos_s3/pmu/
m4_mem_ctrl_0.rs

1#[doc = "Register `M4_MEM_CTRL_0` reader"]
2pub struct R(crate::R<M4_MEM_CTRL_0_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<M4_MEM_CTRL_0_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<M4_MEM_CTRL_0_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<M4_MEM_CTRL_0_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `M4_MEM_CTRL_0` writer"]
17pub struct W(crate::W<M4_MEM_CTRL_0_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<M4_MEM_CTRL_0_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<M4_MEM_CTRL_0_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<M4_MEM_CTRL_0_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Control DS pin of 32KB SRAM Instance 0 on M4 subsystem\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum CTRL_M4_SRAM_DS_0_A {
40    #[doc = "0: Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
41    DISABLE_DEEP_SLEEP = 0,
42    #[doc = "1: Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
43    ENABLE_DEEP_SLEEP = 1,
44}
45impl From<CTRL_M4_SRAM_DS_0_A> for bool {
46    #[inline(always)]
47    fn from(variant: CTRL_M4_SRAM_DS_0_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `CTRL_M4_SRAM_DS_0` reader - Control DS pin of 32KB SRAM Instance 0 on M4 subsystem"]
52pub struct CTRL_M4_SRAM_DS_0_R(crate::FieldReader<bool, CTRL_M4_SRAM_DS_0_A>);
53impl CTRL_M4_SRAM_DS_0_R {
54    #[inline(always)]
55    pub(crate) fn new(bits: bool) -> Self {
56        CTRL_M4_SRAM_DS_0_R(crate::FieldReader::new(bits))
57    }
58    #[doc = r"Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> CTRL_M4_SRAM_DS_0_A {
61        match self.bits {
62            false => CTRL_M4_SRAM_DS_0_A::DISABLE_DEEP_SLEEP,
63            true => CTRL_M4_SRAM_DS_0_A::ENABLE_DEEP_SLEEP,
64        }
65    }
66    #[doc = "Checks if the value of the field is `DISABLE_DEEP_SLEEP`"]
67    #[inline(always)]
68    pub fn is_disable_deep_sleep(&self) -> bool {
69        **self == CTRL_M4_SRAM_DS_0_A::DISABLE_DEEP_SLEEP
70    }
71    #[doc = "Checks if the value of the field is `ENABLE_DEEP_SLEEP`"]
72    #[inline(always)]
73    pub fn is_enable_deep_sleep(&self) -> bool {
74        **self == CTRL_M4_SRAM_DS_0_A::ENABLE_DEEP_SLEEP
75    }
76}
77impl core::ops::Deref for CTRL_M4_SRAM_DS_0_R {
78    type Target = crate::FieldReader<bool, CTRL_M4_SRAM_DS_0_A>;
79    #[inline(always)]
80    fn deref(&self) -> &Self::Target {
81        &self.0
82    }
83}
84#[doc = "Field `CTRL_M4_SRAM_DS_0` writer - Control DS pin of 32KB SRAM Instance 0 on M4 subsystem"]
85pub struct CTRL_M4_SRAM_DS_0_W<'a> {
86    w: &'a mut W,
87}
88impl<'a> CTRL_M4_SRAM_DS_0_W<'a> {
89    #[doc = r"Writes `variant` to the field"]
90    #[inline(always)]
91    pub fn variant(self, variant: CTRL_M4_SRAM_DS_0_A) -> &'a mut W {
92        self.bit(variant.into())
93    }
94    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
95    #[inline(always)]
96    pub fn disable_deep_sleep(self) -> &'a mut W {
97        self.variant(CTRL_M4_SRAM_DS_0_A::DISABLE_DEEP_SLEEP)
98    }
99    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
100    #[inline(always)]
101    pub fn enable_deep_sleep(self) -> &'a mut W {
102        self.variant(CTRL_M4_SRAM_DS_0_A::ENABLE_DEEP_SLEEP)
103    }
104    #[doc = r"Sets the field bit"]
105    #[inline(always)]
106    pub fn set_bit(self) -> &'a mut W {
107        self.bit(true)
108    }
109    #[doc = r"Clears the field bit"]
110    #[inline(always)]
111    pub fn clear_bit(self) -> &'a mut W {
112        self.bit(false)
113    }
114    #[doc = r"Writes raw bits to the field"]
115    #[inline(always)]
116    pub fn bit(self, value: bool) -> &'a mut W {
117        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
118        self.w
119    }
120}
121#[doc = "Control DS pin of 32KB SRAM Instance 1 on M4 subsystem"]
122pub type CTRL_M4_SRAM_DS_1_A = CTRL_M4_SRAM_DS_0_A;
123#[doc = "Field `CTRL_M4_SRAM_DS_1` reader - Control DS pin of 32KB SRAM Instance 1 on M4 subsystem"]
124pub type CTRL_M4_SRAM_DS_1_R = CTRL_M4_SRAM_DS_0_R;
125#[doc = "Field `CTRL_M4_SRAM_DS_1` writer - Control DS pin of 32KB SRAM Instance 1 on M4 subsystem"]
126pub struct CTRL_M4_SRAM_DS_1_W<'a> {
127    w: &'a mut W,
128}
129impl<'a> CTRL_M4_SRAM_DS_1_W<'a> {
130    #[doc = r"Writes `variant` to the field"]
131    #[inline(always)]
132    pub fn variant(self, variant: CTRL_M4_SRAM_DS_1_A) -> &'a mut W {
133        self.bit(variant.into())
134    }
135    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
136    #[inline(always)]
137    pub fn disable_deep_sleep(self) -> &'a mut W {
138        self.variant(CTRL_M4_SRAM_DS_1_A::DISABLE_DEEP_SLEEP)
139    }
140    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
141    #[inline(always)]
142    pub fn enable_deep_sleep(self) -> &'a mut W {
143        self.variant(CTRL_M4_SRAM_DS_1_A::ENABLE_DEEP_SLEEP)
144    }
145    #[doc = r"Sets the field bit"]
146    #[inline(always)]
147    pub fn set_bit(self) -> &'a mut W {
148        self.bit(true)
149    }
150    #[doc = r"Clears the field bit"]
151    #[inline(always)]
152    pub fn clear_bit(self) -> &'a mut W {
153        self.bit(false)
154    }
155    #[doc = r"Writes raw bits to the field"]
156    #[inline(always)]
157    pub fn bit(self, value: bool) -> &'a mut W {
158        self.w.bits =
159            (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
160        self.w
161    }
162}
163#[doc = "Control DS pin of 32KB SRAM Instance 2 on M4 subsystem"]
164pub type CTRL_M4_SRAM_DS_2_A = CTRL_M4_SRAM_DS_0_A;
165#[doc = "Field `CTRL_M4_SRAM_DS_2` reader - Control DS pin of 32KB SRAM Instance 2 on M4 subsystem"]
166pub type CTRL_M4_SRAM_DS_2_R = CTRL_M4_SRAM_DS_0_R;
167#[doc = "Field `CTRL_M4_SRAM_DS_2` writer - Control DS pin of 32KB SRAM Instance 2 on M4 subsystem"]
168pub struct CTRL_M4_SRAM_DS_2_W<'a> {
169    w: &'a mut W,
170}
171impl<'a> CTRL_M4_SRAM_DS_2_W<'a> {
172    #[doc = r"Writes `variant` to the field"]
173    #[inline(always)]
174    pub fn variant(self, variant: CTRL_M4_SRAM_DS_2_A) -> &'a mut W {
175        self.bit(variant.into())
176    }
177    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
178    #[inline(always)]
179    pub fn disable_deep_sleep(self) -> &'a mut W {
180        self.variant(CTRL_M4_SRAM_DS_2_A::DISABLE_DEEP_SLEEP)
181    }
182    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
183    #[inline(always)]
184    pub fn enable_deep_sleep(self) -> &'a mut W {
185        self.variant(CTRL_M4_SRAM_DS_2_A::ENABLE_DEEP_SLEEP)
186    }
187    #[doc = r"Sets the field bit"]
188    #[inline(always)]
189    pub fn set_bit(self) -> &'a mut W {
190        self.bit(true)
191    }
192    #[doc = r"Clears the field bit"]
193    #[inline(always)]
194    pub fn clear_bit(self) -> &'a mut W {
195        self.bit(false)
196    }
197    #[doc = r"Writes raw bits to the field"]
198    #[inline(always)]
199    pub fn bit(self, value: bool) -> &'a mut W {
200        self.w.bits =
201            (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
202        self.w
203    }
204}
205#[doc = "Control DS pin of 32KB SRAM Instance 3 on M4 subsystem"]
206pub type CTRL_M4_SRAM_DS_3_A = CTRL_M4_SRAM_DS_0_A;
207#[doc = "Field `CTRL_M4_SRAM_DS_3` reader - Control DS pin of 32KB SRAM Instance 3 on M4 subsystem"]
208pub type CTRL_M4_SRAM_DS_3_R = CTRL_M4_SRAM_DS_0_R;
209#[doc = "Field `CTRL_M4_SRAM_DS_3` writer - Control DS pin of 32KB SRAM Instance 3 on M4 subsystem"]
210pub struct CTRL_M4_SRAM_DS_3_W<'a> {
211    w: &'a mut W,
212}
213impl<'a> CTRL_M4_SRAM_DS_3_W<'a> {
214    #[doc = r"Writes `variant` to the field"]
215    #[inline(always)]
216    pub fn variant(self, variant: CTRL_M4_SRAM_DS_3_A) -> &'a mut W {
217        self.bit(variant.into())
218    }
219    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
220    #[inline(always)]
221    pub fn disable_deep_sleep(self) -> &'a mut W {
222        self.variant(CTRL_M4_SRAM_DS_3_A::DISABLE_DEEP_SLEEP)
223    }
224    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
225    #[inline(always)]
226    pub fn enable_deep_sleep(self) -> &'a mut W {
227        self.variant(CTRL_M4_SRAM_DS_3_A::ENABLE_DEEP_SLEEP)
228    }
229    #[doc = r"Sets the field bit"]
230    #[inline(always)]
231    pub fn set_bit(self) -> &'a mut W {
232        self.bit(true)
233    }
234    #[doc = r"Clears the field bit"]
235    #[inline(always)]
236    pub fn clear_bit(self) -> &'a mut W {
237        self.bit(false)
238    }
239    #[doc = r"Writes raw bits to the field"]
240    #[inline(always)]
241    pub fn bit(self, value: bool) -> &'a mut W {
242        self.w.bits =
243            (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
244        self.w
245    }
246}
247#[doc = "Control DS pin of 32KB SRAM Instance 4 on M4 subsystem"]
248pub type CTRL_M4_SRAM_DS_4_A = CTRL_M4_SRAM_DS_0_A;
249#[doc = "Field `CTRL_M4_SRAM_DS_4` reader - Control DS pin of 32KB SRAM Instance 4 on M4 subsystem"]
250pub type CTRL_M4_SRAM_DS_4_R = CTRL_M4_SRAM_DS_0_R;
251#[doc = "Field `CTRL_M4_SRAM_DS_4` writer - Control DS pin of 32KB SRAM Instance 4 on M4 subsystem"]
252pub struct CTRL_M4_SRAM_DS_4_W<'a> {
253    w: &'a mut W,
254}
255impl<'a> CTRL_M4_SRAM_DS_4_W<'a> {
256    #[doc = r"Writes `variant` to the field"]
257    #[inline(always)]
258    pub fn variant(self, variant: CTRL_M4_SRAM_DS_4_A) -> &'a mut W {
259        self.bit(variant.into())
260    }
261    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
262    #[inline(always)]
263    pub fn disable_deep_sleep(self) -> &'a mut W {
264        self.variant(CTRL_M4_SRAM_DS_4_A::DISABLE_DEEP_SLEEP)
265    }
266    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
267    #[inline(always)]
268    pub fn enable_deep_sleep(self) -> &'a mut W {
269        self.variant(CTRL_M4_SRAM_DS_4_A::ENABLE_DEEP_SLEEP)
270    }
271    #[doc = r"Sets the field bit"]
272    #[inline(always)]
273    pub fn set_bit(self) -> &'a mut W {
274        self.bit(true)
275    }
276    #[doc = r"Clears the field bit"]
277    #[inline(always)]
278    pub fn clear_bit(self) -> &'a mut W {
279        self.bit(false)
280    }
281    #[doc = r"Writes raw bits to the field"]
282    #[inline(always)]
283    pub fn bit(self, value: bool) -> &'a mut W {
284        self.w.bits =
285            (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
286        self.w
287    }
288}
289#[doc = "Control DS pin of 32KB SRAM Instance 5 on M4 subsystem"]
290pub type CTRL_M4_SRAM_DS_5_A = CTRL_M4_SRAM_DS_0_A;
291#[doc = "Field `CTRL_M4_SRAM_DS_5` reader - Control DS pin of 32KB SRAM Instance 5 on M4 subsystem"]
292pub type CTRL_M4_SRAM_DS_5_R = CTRL_M4_SRAM_DS_0_R;
293#[doc = "Field `CTRL_M4_SRAM_DS_5` writer - Control DS pin of 32KB SRAM Instance 5 on M4 subsystem"]
294pub struct CTRL_M4_SRAM_DS_5_W<'a> {
295    w: &'a mut W,
296}
297impl<'a> CTRL_M4_SRAM_DS_5_W<'a> {
298    #[doc = r"Writes `variant` to the field"]
299    #[inline(always)]
300    pub fn variant(self, variant: CTRL_M4_SRAM_DS_5_A) -> &'a mut W {
301        self.bit(variant.into())
302    }
303    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
304    #[inline(always)]
305    pub fn disable_deep_sleep(self) -> &'a mut W {
306        self.variant(CTRL_M4_SRAM_DS_5_A::DISABLE_DEEP_SLEEP)
307    }
308    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
309    #[inline(always)]
310    pub fn enable_deep_sleep(self) -> &'a mut W {
311        self.variant(CTRL_M4_SRAM_DS_5_A::ENABLE_DEEP_SLEEP)
312    }
313    #[doc = r"Sets the field bit"]
314    #[inline(always)]
315    pub fn set_bit(self) -> &'a mut W {
316        self.bit(true)
317    }
318    #[doc = r"Clears the field bit"]
319    #[inline(always)]
320    pub fn clear_bit(self) -> &'a mut W {
321        self.bit(false)
322    }
323    #[doc = r"Writes raw bits to the field"]
324    #[inline(always)]
325    pub fn bit(self, value: bool) -> &'a mut W {
326        self.w.bits =
327            (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
328        self.w
329    }
330}
331#[doc = "Control DS pin of 32KB SRAM Instance 6 on M4 subsystem"]
332pub type CTRL_M4_SRAM_DS_6_A = CTRL_M4_SRAM_DS_0_A;
333#[doc = "Field `CTRL_M4_SRAM_DS_6` reader - Control DS pin of 32KB SRAM Instance 6 on M4 subsystem"]
334pub type CTRL_M4_SRAM_DS_6_R = CTRL_M4_SRAM_DS_0_R;
335#[doc = "Field `CTRL_M4_SRAM_DS_6` writer - Control DS pin of 32KB SRAM Instance 6 on M4 subsystem"]
336pub struct CTRL_M4_SRAM_DS_6_W<'a> {
337    w: &'a mut W,
338}
339impl<'a> CTRL_M4_SRAM_DS_6_W<'a> {
340    #[doc = r"Writes `variant` to the field"]
341    #[inline(always)]
342    pub fn variant(self, variant: CTRL_M4_SRAM_DS_6_A) -> &'a mut W {
343        self.bit(variant.into())
344    }
345    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
346    #[inline(always)]
347    pub fn disable_deep_sleep(self) -> &'a mut W {
348        self.variant(CTRL_M4_SRAM_DS_6_A::DISABLE_DEEP_SLEEP)
349    }
350    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
351    #[inline(always)]
352    pub fn enable_deep_sleep(self) -> &'a mut W {
353        self.variant(CTRL_M4_SRAM_DS_6_A::ENABLE_DEEP_SLEEP)
354    }
355    #[doc = r"Sets the field bit"]
356    #[inline(always)]
357    pub fn set_bit(self) -> &'a mut W {
358        self.bit(true)
359    }
360    #[doc = r"Clears the field bit"]
361    #[inline(always)]
362    pub fn clear_bit(self) -> &'a mut W {
363        self.bit(false)
364    }
365    #[doc = r"Writes raw bits to the field"]
366    #[inline(always)]
367    pub fn bit(self, value: bool) -> &'a mut W {
368        self.w.bits =
369            (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
370        self.w
371    }
372}
373#[doc = "Control DS pin of 32KB SRAM Instance 7 on M4 subsystem"]
374pub type CTRL_M4_SRAM_DS_7_A = CTRL_M4_SRAM_DS_0_A;
375#[doc = "Field `CTRL_M4_SRAM_DS_7` reader - Control DS pin of 32KB SRAM Instance 7 on M4 subsystem"]
376pub type CTRL_M4_SRAM_DS_7_R = CTRL_M4_SRAM_DS_0_R;
377#[doc = "Field `CTRL_M4_SRAM_DS_7` writer - Control DS pin of 32KB SRAM Instance 7 on M4 subsystem"]
378pub struct CTRL_M4_SRAM_DS_7_W<'a> {
379    w: &'a mut W,
380}
381impl<'a> CTRL_M4_SRAM_DS_7_W<'a> {
382    #[doc = r"Writes `variant` to the field"]
383    #[inline(always)]
384    pub fn variant(self, variant: CTRL_M4_SRAM_DS_7_A) -> &'a mut W {
385        self.bit(variant.into())
386    }
387    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
388    #[inline(always)]
389    pub fn disable_deep_sleep(self) -> &'a mut W {
390        self.variant(CTRL_M4_SRAM_DS_7_A::DISABLE_DEEP_SLEEP)
391    }
392    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
393    #[inline(always)]
394    pub fn enable_deep_sleep(self) -> &'a mut W {
395        self.variant(CTRL_M4_SRAM_DS_7_A::ENABLE_DEEP_SLEEP)
396    }
397    #[doc = r"Sets the field bit"]
398    #[inline(always)]
399    pub fn set_bit(self) -> &'a mut W {
400        self.bit(true)
401    }
402    #[doc = r"Clears the field bit"]
403    #[inline(always)]
404    pub fn clear_bit(self) -> &'a mut W {
405        self.bit(false)
406    }
407    #[doc = r"Writes raw bits to the field"]
408    #[inline(always)]
409    pub fn bit(self, value: bool) -> &'a mut W {
410        self.w.bits =
411            (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
412        self.w
413    }
414}
415#[doc = "Control DS pin of 32KB SRAM Instance 8 on M4 subsystem"]
416pub type CTRL_M4_SRAM_DS_8_A = CTRL_M4_SRAM_DS_0_A;
417#[doc = "Field `CTRL_M4_SRAM_DS_8` reader - Control DS pin of 32KB SRAM Instance 8 on M4 subsystem"]
418pub type CTRL_M4_SRAM_DS_8_R = CTRL_M4_SRAM_DS_0_R;
419#[doc = "Field `CTRL_M4_SRAM_DS_8` writer - Control DS pin of 32KB SRAM Instance 8 on M4 subsystem"]
420pub struct CTRL_M4_SRAM_DS_8_W<'a> {
421    w: &'a mut W,
422}
423impl<'a> CTRL_M4_SRAM_DS_8_W<'a> {
424    #[doc = r"Writes `variant` to the field"]
425    #[inline(always)]
426    pub fn variant(self, variant: CTRL_M4_SRAM_DS_8_A) -> &'a mut W {
427        self.bit(variant.into())
428    }
429    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
430    #[inline(always)]
431    pub fn disable_deep_sleep(self) -> &'a mut W {
432        self.variant(CTRL_M4_SRAM_DS_8_A::DISABLE_DEEP_SLEEP)
433    }
434    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
435    #[inline(always)]
436    pub fn enable_deep_sleep(self) -> &'a mut W {
437        self.variant(CTRL_M4_SRAM_DS_8_A::ENABLE_DEEP_SLEEP)
438    }
439    #[doc = r"Sets the field bit"]
440    #[inline(always)]
441    pub fn set_bit(self) -> &'a mut W {
442        self.bit(true)
443    }
444    #[doc = r"Clears the field bit"]
445    #[inline(always)]
446    pub fn clear_bit(self) -> &'a mut W {
447        self.bit(false)
448    }
449    #[doc = r"Writes raw bits to the field"]
450    #[inline(always)]
451    pub fn bit(self, value: bool) -> &'a mut W {
452        self.w.bits =
453            (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
454        self.w
455    }
456}
457#[doc = "Control DS pin of 32KB SRAM Instance 9 on M4 subsystem"]
458pub type CTRL_M4_SRAM_DS_9_A = CTRL_M4_SRAM_DS_0_A;
459#[doc = "Field `CTRL_M4_SRAM_DS_9` reader - Control DS pin of 32KB SRAM Instance 9 on M4 subsystem"]
460pub type CTRL_M4_SRAM_DS_9_R = CTRL_M4_SRAM_DS_0_R;
461#[doc = "Field `CTRL_M4_SRAM_DS_9` writer - Control DS pin of 32KB SRAM Instance 9 on M4 subsystem"]
462pub struct CTRL_M4_SRAM_DS_9_W<'a> {
463    w: &'a mut W,
464}
465impl<'a> CTRL_M4_SRAM_DS_9_W<'a> {
466    #[doc = r"Writes `variant` to the field"]
467    #[inline(always)]
468    pub fn variant(self, variant: CTRL_M4_SRAM_DS_9_A) -> &'a mut W {
469        self.bit(variant.into())
470    }
471    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
472    #[inline(always)]
473    pub fn disable_deep_sleep(self) -> &'a mut W {
474        self.variant(CTRL_M4_SRAM_DS_9_A::DISABLE_DEEP_SLEEP)
475    }
476    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
477    #[inline(always)]
478    pub fn enable_deep_sleep(self) -> &'a mut W {
479        self.variant(CTRL_M4_SRAM_DS_9_A::ENABLE_DEEP_SLEEP)
480    }
481    #[doc = r"Sets the field bit"]
482    #[inline(always)]
483    pub fn set_bit(self) -> &'a mut W {
484        self.bit(true)
485    }
486    #[doc = r"Clears the field bit"]
487    #[inline(always)]
488    pub fn clear_bit(self) -> &'a mut W {
489        self.bit(false)
490    }
491    #[doc = r"Writes raw bits to the field"]
492    #[inline(always)]
493    pub fn bit(self, value: bool) -> &'a mut W {
494        self.w.bits =
495            (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
496        self.w
497    }
498}
499#[doc = "Control DS pin of 32KB SRAM Instance 10 on M4 subsystem"]
500pub type CTRL_M4_SRAM_DS_10_A = CTRL_M4_SRAM_DS_0_A;
501#[doc = "Field `CTRL_M4_SRAM_DS_10` reader - Control DS pin of 32KB SRAM Instance 10 on M4 subsystem"]
502pub type CTRL_M4_SRAM_DS_10_R = CTRL_M4_SRAM_DS_0_R;
503#[doc = "Field `CTRL_M4_SRAM_DS_10` writer - Control DS pin of 32KB SRAM Instance 10 on M4 subsystem"]
504pub struct CTRL_M4_SRAM_DS_10_W<'a> {
505    w: &'a mut W,
506}
507impl<'a> CTRL_M4_SRAM_DS_10_W<'a> {
508    #[doc = r"Writes `variant` to the field"]
509    #[inline(always)]
510    pub fn variant(self, variant: CTRL_M4_SRAM_DS_10_A) -> &'a mut W {
511        self.bit(variant.into())
512    }
513    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
514    #[inline(always)]
515    pub fn disable_deep_sleep(self) -> &'a mut W {
516        self.variant(CTRL_M4_SRAM_DS_10_A::DISABLE_DEEP_SLEEP)
517    }
518    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
519    #[inline(always)]
520    pub fn enable_deep_sleep(self) -> &'a mut W {
521        self.variant(CTRL_M4_SRAM_DS_10_A::ENABLE_DEEP_SLEEP)
522    }
523    #[doc = r"Sets the field bit"]
524    #[inline(always)]
525    pub fn set_bit(self) -> &'a mut W {
526        self.bit(true)
527    }
528    #[doc = r"Clears the field bit"]
529    #[inline(always)]
530    pub fn clear_bit(self) -> &'a mut W {
531        self.bit(false)
532    }
533    #[doc = r"Writes raw bits to the field"]
534    #[inline(always)]
535    pub fn bit(self, value: bool) -> &'a mut W {
536        self.w.bits =
537            (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
538        self.w
539    }
540}
541#[doc = "Control DS pin of 32KB SRAM Instance 11 on M4 subsystem"]
542pub type CTRL_M4_SRAM_DS_11_A = CTRL_M4_SRAM_DS_0_A;
543#[doc = "Field `CTRL_M4_SRAM_DS_11` reader - Control DS pin of 32KB SRAM Instance 11 on M4 subsystem"]
544pub type CTRL_M4_SRAM_DS_11_R = CTRL_M4_SRAM_DS_0_R;
545#[doc = "Field `CTRL_M4_SRAM_DS_11` writer - Control DS pin of 32KB SRAM Instance 11 on M4 subsystem"]
546pub struct CTRL_M4_SRAM_DS_11_W<'a> {
547    w: &'a mut W,
548}
549impl<'a> CTRL_M4_SRAM_DS_11_W<'a> {
550    #[doc = r"Writes `variant` to the field"]
551    #[inline(always)]
552    pub fn variant(self, variant: CTRL_M4_SRAM_DS_11_A) -> &'a mut W {
553        self.bit(variant.into())
554    }
555    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
556    #[inline(always)]
557    pub fn disable_deep_sleep(self) -> &'a mut W {
558        self.variant(CTRL_M4_SRAM_DS_11_A::DISABLE_DEEP_SLEEP)
559    }
560    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
561    #[inline(always)]
562    pub fn enable_deep_sleep(self) -> &'a mut W {
563        self.variant(CTRL_M4_SRAM_DS_11_A::ENABLE_DEEP_SLEEP)
564    }
565    #[doc = r"Sets the field bit"]
566    #[inline(always)]
567    pub fn set_bit(self) -> &'a mut W {
568        self.bit(true)
569    }
570    #[doc = r"Clears the field bit"]
571    #[inline(always)]
572    pub fn clear_bit(self) -> &'a mut W {
573        self.bit(false)
574    }
575    #[doc = r"Writes raw bits to the field"]
576    #[inline(always)]
577    pub fn bit(self, value: bool) -> &'a mut W {
578        self.w.bits =
579            (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
580        self.w
581    }
582}
583#[doc = "Control DS pin of 32KB SRAM Instance 12 on M4 subsystem"]
584pub type CTRL_M4_SRAM_DS_12_A = CTRL_M4_SRAM_DS_0_A;
585#[doc = "Field `CTRL_M4_SRAM_DS_12` reader - Control DS pin of 32KB SRAM Instance 12 on M4 subsystem"]
586pub type CTRL_M4_SRAM_DS_12_R = CTRL_M4_SRAM_DS_0_R;
587#[doc = "Field `CTRL_M4_SRAM_DS_12` writer - Control DS pin of 32KB SRAM Instance 12 on M4 subsystem"]
588pub struct CTRL_M4_SRAM_DS_12_W<'a> {
589    w: &'a mut W,
590}
591impl<'a> CTRL_M4_SRAM_DS_12_W<'a> {
592    #[doc = r"Writes `variant` to the field"]
593    #[inline(always)]
594    pub fn variant(self, variant: CTRL_M4_SRAM_DS_12_A) -> &'a mut W {
595        self.bit(variant.into())
596    }
597    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
598    #[inline(always)]
599    pub fn disable_deep_sleep(self) -> &'a mut W {
600        self.variant(CTRL_M4_SRAM_DS_12_A::DISABLE_DEEP_SLEEP)
601    }
602    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
603    #[inline(always)]
604    pub fn enable_deep_sleep(self) -> &'a mut W {
605        self.variant(CTRL_M4_SRAM_DS_12_A::ENABLE_DEEP_SLEEP)
606    }
607    #[doc = r"Sets the field bit"]
608    #[inline(always)]
609    pub fn set_bit(self) -> &'a mut W {
610        self.bit(true)
611    }
612    #[doc = r"Clears the field bit"]
613    #[inline(always)]
614    pub fn clear_bit(self) -> &'a mut W {
615        self.bit(false)
616    }
617    #[doc = r"Writes raw bits to the field"]
618    #[inline(always)]
619    pub fn bit(self, value: bool) -> &'a mut W {
620        self.w.bits =
621            (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
622        self.w
623    }
624}
625#[doc = "Control DS pin of 32KB SRAM Instance 13 on M4 subsystem"]
626pub type CTRL_M4_SRAM_DS_13_A = CTRL_M4_SRAM_DS_0_A;
627#[doc = "Field `CTRL_M4_SRAM_DS_13` reader - Control DS pin of 32KB SRAM Instance 13 on M4 subsystem"]
628pub type CTRL_M4_SRAM_DS_13_R = CTRL_M4_SRAM_DS_0_R;
629#[doc = "Field `CTRL_M4_SRAM_DS_13` writer - Control DS pin of 32KB SRAM Instance 13 on M4 subsystem"]
630pub struct CTRL_M4_SRAM_DS_13_W<'a> {
631    w: &'a mut W,
632}
633impl<'a> CTRL_M4_SRAM_DS_13_W<'a> {
634    #[doc = r"Writes `variant` to the field"]
635    #[inline(always)]
636    pub fn variant(self, variant: CTRL_M4_SRAM_DS_13_A) -> &'a mut W {
637        self.bit(variant.into())
638    }
639    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
640    #[inline(always)]
641    pub fn disable_deep_sleep(self) -> &'a mut W {
642        self.variant(CTRL_M4_SRAM_DS_13_A::DISABLE_DEEP_SLEEP)
643    }
644    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
645    #[inline(always)]
646    pub fn enable_deep_sleep(self) -> &'a mut W {
647        self.variant(CTRL_M4_SRAM_DS_13_A::ENABLE_DEEP_SLEEP)
648    }
649    #[doc = r"Sets the field bit"]
650    #[inline(always)]
651    pub fn set_bit(self) -> &'a mut W {
652        self.bit(true)
653    }
654    #[doc = r"Clears the field bit"]
655    #[inline(always)]
656    pub fn clear_bit(self) -> &'a mut W {
657        self.bit(false)
658    }
659    #[doc = r"Writes raw bits to the field"]
660    #[inline(always)]
661    pub fn bit(self, value: bool) -> &'a mut W {
662        self.w.bits =
663            (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
664        self.w
665    }
666}
667#[doc = "Control DS pin of 32KB SRAM Instance 14 on M4 subsystem"]
668pub type CTRL_M4_SRAM_DS_14_A = CTRL_M4_SRAM_DS_0_A;
669#[doc = "Field `CTRL_M4_SRAM_DS_14` reader - Control DS pin of 32KB SRAM Instance 14 on M4 subsystem"]
670pub type CTRL_M4_SRAM_DS_14_R = CTRL_M4_SRAM_DS_0_R;
671#[doc = "Field `CTRL_M4_SRAM_DS_14` writer - Control DS pin of 32KB SRAM Instance 14 on M4 subsystem"]
672pub struct CTRL_M4_SRAM_DS_14_W<'a> {
673    w: &'a mut W,
674}
675impl<'a> CTRL_M4_SRAM_DS_14_W<'a> {
676    #[doc = r"Writes `variant` to the field"]
677    #[inline(always)]
678    pub fn variant(self, variant: CTRL_M4_SRAM_DS_14_A) -> &'a mut W {
679        self.bit(variant.into())
680    }
681    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
682    #[inline(always)]
683    pub fn disable_deep_sleep(self) -> &'a mut W {
684        self.variant(CTRL_M4_SRAM_DS_14_A::DISABLE_DEEP_SLEEP)
685    }
686    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
687    #[inline(always)]
688    pub fn enable_deep_sleep(self) -> &'a mut W {
689        self.variant(CTRL_M4_SRAM_DS_14_A::ENABLE_DEEP_SLEEP)
690    }
691    #[doc = r"Sets the field bit"]
692    #[inline(always)]
693    pub fn set_bit(self) -> &'a mut W {
694        self.bit(true)
695    }
696    #[doc = r"Clears the field bit"]
697    #[inline(always)]
698    pub fn clear_bit(self) -> &'a mut W {
699        self.bit(false)
700    }
701    #[doc = r"Writes raw bits to the field"]
702    #[inline(always)]
703    pub fn bit(self, value: bool) -> &'a mut W {
704        self.w.bits =
705            (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
706        self.w
707    }
708}
709#[doc = "Control DS pin of 32KB SRAM Instance 15 on M4 subsystem"]
710pub type CTRL_M4_SRAM_DS_15_A = CTRL_M4_SRAM_DS_0_A;
711#[doc = "Field `CTRL_M4_SRAM_DS_15` reader - Control DS pin of 32KB SRAM Instance 15 on M4 subsystem"]
712pub type CTRL_M4_SRAM_DS_15_R = CTRL_M4_SRAM_DS_0_R;
713#[doc = "Field `CTRL_M4_SRAM_DS_15` writer - Control DS pin of 32KB SRAM Instance 15 on M4 subsystem"]
714pub struct CTRL_M4_SRAM_DS_15_W<'a> {
715    w: &'a mut W,
716}
717impl<'a> CTRL_M4_SRAM_DS_15_W<'a> {
718    #[doc = r"Writes `variant` to the field"]
719    #[inline(always)]
720    pub fn variant(self, variant: CTRL_M4_SRAM_DS_15_A) -> &'a mut W {
721        self.bit(variant.into())
722    }
723    #[doc = "Disable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
724    #[inline(always)]
725    pub fn disable_deep_sleep(self) -> &'a mut W {
726        self.variant(CTRL_M4_SRAM_DS_15_A::DISABLE_DEEP_SLEEP)
727    }
728    #[doc = "Enable the Deep Sleep function of SRAM Macro, Memory content will be kept."]
729    #[inline(always)]
730    pub fn enable_deep_sleep(self) -> &'a mut W {
731        self.variant(CTRL_M4_SRAM_DS_15_A::ENABLE_DEEP_SLEEP)
732    }
733    #[doc = r"Sets the field bit"]
734    #[inline(always)]
735    pub fn set_bit(self) -> &'a mut W {
736        self.bit(true)
737    }
738    #[doc = r"Clears the field bit"]
739    #[inline(always)]
740    pub fn clear_bit(self) -> &'a mut W {
741        self.bit(false)
742    }
743    #[doc = r"Writes raw bits to the field"]
744    #[inline(always)]
745    pub fn bit(self, value: bool) -> &'a mut W {
746        self.w.bits =
747            (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
748        self.w
749    }
750}
751impl R {
752    #[doc = "Bit 0 - Control DS pin of 32KB SRAM Instance 0 on M4 subsystem"]
753    #[inline(always)]
754    pub fn ctrl_m4_sram_ds_0(&self) -> CTRL_M4_SRAM_DS_0_R {
755        CTRL_M4_SRAM_DS_0_R::new((self.bits & 0x01) != 0)
756    }
757    #[doc = "Bit 1 - Control DS pin of 32KB SRAM Instance 1 on M4 subsystem"]
758    #[inline(always)]
759    pub fn ctrl_m4_sram_ds_1(&self) -> CTRL_M4_SRAM_DS_1_R {
760        CTRL_M4_SRAM_DS_1_R::new(((self.bits >> 1) & 0x01) != 0)
761    }
762    #[doc = "Bit 2 - Control DS pin of 32KB SRAM Instance 2 on M4 subsystem"]
763    #[inline(always)]
764    pub fn ctrl_m4_sram_ds_2(&self) -> CTRL_M4_SRAM_DS_2_R {
765        CTRL_M4_SRAM_DS_2_R::new(((self.bits >> 2) & 0x01) != 0)
766    }
767    #[doc = "Bit 3 - Control DS pin of 32KB SRAM Instance 3 on M4 subsystem"]
768    #[inline(always)]
769    pub fn ctrl_m4_sram_ds_3(&self) -> CTRL_M4_SRAM_DS_3_R {
770        CTRL_M4_SRAM_DS_3_R::new(((self.bits >> 3) & 0x01) != 0)
771    }
772    #[doc = "Bit 4 - Control DS pin of 32KB SRAM Instance 4 on M4 subsystem"]
773    #[inline(always)]
774    pub fn ctrl_m4_sram_ds_4(&self) -> CTRL_M4_SRAM_DS_4_R {
775        CTRL_M4_SRAM_DS_4_R::new(((self.bits >> 4) & 0x01) != 0)
776    }
777    #[doc = "Bit 5 - Control DS pin of 32KB SRAM Instance 5 on M4 subsystem"]
778    #[inline(always)]
779    pub fn ctrl_m4_sram_ds_5(&self) -> CTRL_M4_SRAM_DS_5_R {
780        CTRL_M4_SRAM_DS_5_R::new(((self.bits >> 5) & 0x01) != 0)
781    }
782    #[doc = "Bit 6 - Control DS pin of 32KB SRAM Instance 6 on M4 subsystem"]
783    #[inline(always)]
784    pub fn ctrl_m4_sram_ds_6(&self) -> CTRL_M4_SRAM_DS_6_R {
785        CTRL_M4_SRAM_DS_6_R::new(((self.bits >> 6) & 0x01) != 0)
786    }
787    #[doc = "Bit 7 - Control DS pin of 32KB SRAM Instance 7 on M4 subsystem"]
788    #[inline(always)]
789    pub fn ctrl_m4_sram_ds_7(&self) -> CTRL_M4_SRAM_DS_7_R {
790        CTRL_M4_SRAM_DS_7_R::new(((self.bits >> 7) & 0x01) != 0)
791    }
792    #[doc = "Bit 8 - Control DS pin of 32KB SRAM Instance 8 on M4 subsystem"]
793    #[inline(always)]
794    pub fn ctrl_m4_sram_ds_8(&self) -> CTRL_M4_SRAM_DS_8_R {
795        CTRL_M4_SRAM_DS_8_R::new(((self.bits >> 8) & 0x01) != 0)
796    }
797    #[doc = "Bit 9 - Control DS pin of 32KB SRAM Instance 9 on M4 subsystem"]
798    #[inline(always)]
799    pub fn ctrl_m4_sram_ds_9(&self) -> CTRL_M4_SRAM_DS_9_R {
800        CTRL_M4_SRAM_DS_9_R::new(((self.bits >> 9) & 0x01) != 0)
801    }
802    #[doc = "Bit 10 - Control DS pin of 32KB SRAM Instance 10 on M4 subsystem"]
803    #[inline(always)]
804    pub fn ctrl_m4_sram_ds_10(&self) -> CTRL_M4_SRAM_DS_10_R {
805        CTRL_M4_SRAM_DS_10_R::new(((self.bits >> 10) & 0x01) != 0)
806    }
807    #[doc = "Bit 11 - Control DS pin of 32KB SRAM Instance 11 on M4 subsystem"]
808    #[inline(always)]
809    pub fn ctrl_m4_sram_ds_11(&self) -> CTRL_M4_SRAM_DS_11_R {
810        CTRL_M4_SRAM_DS_11_R::new(((self.bits >> 11) & 0x01) != 0)
811    }
812    #[doc = "Bit 12 - Control DS pin of 32KB SRAM Instance 12 on M4 subsystem"]
813    #[inline(always)]
814    pub fn ctrl_m4_sram_ds_12(&self) -> CTRL_M4_SRAM_DS_12_R {
815        CTRL_M4_SRAM_DS_12_R::new(((self.bits >> 12) & 0x01) != 0)
816    }
817    #[doc = "Bit 13 - Control DS pin of 32KB SRAM Instance 13 on M4 subsystem"]
818    #[inline(always)]
819    pub fn ctrl_m4_sram_ds_13(&self) -> CTRL_M4_SRAM_DS_13_R {
820        CTRL_M4_SRAM_DS_13_R::new(((self.bits >> 13) & 0x01) != 0)
821    }
822    #[doc = "Bit 14 - Control DS pin of 32KB SRAM Instance 14 on M4 subsystem"]
823    #[inline(always)]
824    pub fn ctrl_m4_sram_ds_14(&self) -> CTRL_M4_SRAM_DS_14_R {
825        CTRL_M4_SRAM_DS_14_R::new(((self.bits >> 14) & 0x01) != 0)
826    }
827    #[doc = "Bit 15 - Control DS pin of 32KB SRAM Instance 15 on M4 subsystem"]
828    #[inline(always)]
829    pub fn ctrl_m4_sram_ds_15(&self) -> CTRL_M4_SRAM_DS_15_R {
830        CTRL_M4_SRAM_DS_15_R::new(((self.bits >> 15) & 0x01) != 0)
831    }
832}
833impl W {
834    #[doc = "Bit 0 - Control DS pin of 32KB SRAM Instance 0 on M4 subsystem"]
835    #[inline(always)]
836    pub fn ctrl_m4_sram_ds_0(&mut self) -> CTRL_M4_SRAM_DS_0_W {
837        CTRL_M4_SRAM_DS_0_W { w: self }
838    }
839    #[doc = "Bit 1 - Control DS pin of 32KB SRAM Instance 1 on M4 subsystem"]
840    #[inline(always)]
841    pub fn ctrl_m4_sram_ds_1(&mut self) -> CTRL_M4_SRAM_DS_1_W {
842        CTRL_M4_SRAM_DS_1_W { w: self }
843    }
844    #[doc = "Bit 2 - Control DS pin of 32KB SRAM Instance 2 on M4 subsystem"]
845    #[inline(always)]
846    pub fn ctrl_m4_sram_ds_2(&mut self) -> CTRL_M4_SRAM_DS_2_W {
847        CTRL_M4_SRAM_DS_2_W { w: self }
848    }
849    #[doc = "Bit 3 - Control DS pin of 32KB SRAM Instance 3 on M4 subsystem"]
850    #[inline(always)]
851    pub fn ctrl_m4_sram_ds_3(&mut self) -> CTRL_M4_SRAM_DS_3_W {
852        CTRL_M4_SRAM_DS_3_W { w: self }
853    }
854    #[doc = "Bit 4 - Control DS pin of 32KB SRAM Instance 4 on M4 subsystem"]
855    #[inline(always)]
856    pub fn ctrl_m4_sram_ds_4(&mut self) -> CTRL_M4_SRAM_DS_4_W {
857        CTRL_M4_SRAM_DS_4_W { w: self }
858    }
859    #[doc = "Bit 5 - Control DS pin of 32KB SRAM Instance 5 on M4 subsystem"]
860    #[inline(always)]
861    pub fn ctrl_m4_sram_ds_5(&mut self) -> CTRL_M4_SRAM_DS_5_W {
862        CTRL_M4_SRAM_DS_5_W { w: self }
863    }
864    #[doc = "Bit 6 - Control DS pin of 32KB SRAM Instance 6 on M4 subsystem"]
865    #[inline(always)]
866    pub fn ctrl_m4_sram_ds_6(&mut self) -> CTRL_M4_SRAM_DS_6_W {
867        CTRL_M4_SRAM_DS_6_W { w: self }
868    }
869    #[doc = "Bit 7 - Control DS pin of 32KB SRAM Instance 7 on M4 subsystem"]
870    #[inline(always)]
871    pub fn ctrl_m4_sram_ds_7(&mut self) -> CTRL_M4_SRAM_DS_7_W {
872        CTRL_M4_SRAM_DS_7_W { w: self }
873    }
874    #[doc = "Bit 8 - Control DS pin of 32KB SRAM Instance 8 on M4 subsystem"]
875    #[inline(always)]
876    pub fn ctrl_m4_sram_ds_8(&mut self) -> CTRL_M4_SRAM_DS_8_W {
877        CTRL_M4_SRAM_DS_8_W { w: self }
878    }
879    #[doc = "Bit 9 - Control DS pin of 32KB SRAM Instance 9 on M4 subsystem"]
880    #[inline(always)]
881    pub fn ctrl_m4_sram_ds_9(&mut self) -> CTRL_M4_SRAM_DS_9_W {
882        CTRL_M4_SRAM_DS_9_W { w: self }
883    }
884    #[doc = "Bit 10 - Control DS pin of 32KB SRAM Instance 10 on M4 subsystem"]
885    #[inline(always)]
886    pub fn ctrl_m4_sram_ds_10(&mut self) -> CTRL_M4_SRAM_DS_10_W {
887        CTRL_M4_SRAM_DS_10_W { w: self }
888    }
889    #[doc = "Bit 11 - Control DS pin of 32KB SRAM Instance 11 on M4 subsystem"]
890    #[inline(always)]
891    pub fn ctrl_m4_sram_ds_11(&mut self) -> CTRL_M4_SRAM_DS_11_W {
892        CTRL_M4_SRAM_DS_11_W { w: self }
893    }
894    #[doc = "Bit 12 - Control DS pin of 32KB SRAM Instance 12 on M4 subsystem"]
895    #[inline(always)]
896    pub fn ctrl_m4_sram_ds_12(&mut self) -> CTRL_M4_SRAM_DS_12_W {
897        CTRL_M4_SRAM_DS_12_W { w: self }
898    }
899    #[doc = "Bit 13 - Control DS pin of 32KB SRAM Instance 13 on M4 subsystem"]
900    #[inline(always)]
901    pub fn ctrl_m4_sram_ds_13(&mut self) -> CTRL_M4_SRAM_DS_13_W {
902        CTRL_M4_SRAM_DS_13_W { w: self }
903    }
904    #[doc = "Bit 14 - Control DS pin of 32KB SRAM Instance 14 on M4 subsystem"]
905    #[inline(always)]
906    pub fn ctrl_m4_sram_ds_14(&mut self) -> CTRL_M4_SRAM_DS_14_W {
907        CTRL_M4_SRAM_DS_14_W { w: self }
908    }
909    #[doc = "Bit 15 - Control DS pin of 32KB SRAM Instance 15 on M4 subsystem"]
910    #[inline(always)]
911    pub fn ctrl_m4_sram_ds_15(&mut self) -> CTRL_M4_SRAM_DS_15_W {
912        CTRL_M4_SRAM_DS_15_W { w: self }
913    }
914    #[doc = "Writes raw bits to the register."]
915    #[inline(always)]
916    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
917        self.0.bits(bits);
918        self
919    }
920}
921#[doc = "Control DS pins for different SRAM instances on the M4 subsystem. For each instance: 1'b1 : Enable the Deep Sleep funciton of SRAM Macro, Memory content will be kept. While M4 access the memory in Deep Sleep mode, the HW will clear the corresponding bit.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [m4_mem_ctrl_0](index.html) module"]
922pub struct M4_MEM_CTRL_0_SPEC;
923impl crate::RegisterSpec for M4_MEM_CTRL_0_SPEC {
924    type Ux = u32;
925}
926#[doc = "`read()` method returns [m4_mem_ctrl_0::R](R) reader structure"]
927impl crate::Readable for M4_MEM_CTRL_0_SPEC {
928    type Reader = R;
929}
930#[doc = "`write(|w| ..)` method takes [m4_mem_ctrl_0::W](W) writer structure"]
931impl crate::Writable for M4_MEM_CTRL_0_SPEC {
932    type Writer = W;
933}
934#[doc = "`reset()` method sets M4_MEM_CTRL_0 to value 0xfffe"]
935impl crate::Resettable for M4_MEM_CTRL_0_SPEC {
936    #[inline(always)]
937    fn reset_value() -> Self::Ux {
938        0xfffe
939    }
940}
eos_s3/pmu/m4_mem_ctrl_0.rs

eos_s3/pmu/
m4_mem_ctrl_0.rs
