eos_s3/pmu/
fbvlpmin_width.rs

1#[doc = "Register `FBVLPMinWidth` reader"]
2pub struct R(crate::R<FBVLPMINWIDTH_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FBVLPMINWIDTH_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FBVLPMINWIDTH_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FBVLPMINWIDTH_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `FBVLPMinWidth` writer"]
17pub struct W(crate::W<FBVLPMINWIDTH_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FBVLPMINWIDTH_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FBVLPMINWIDTH_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FBVLPMINWIDTH_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `FBVLPMinWidth` reader - For FB, it required additional IDLE Cylcle from turning off power gates (Power is ON) to ready for normal operation. This is used to defined the # of the IDLE cycles (base on C01 Clock). According to FB spec, it will require 10uS. But for final spec, it should be from FB design team."]
38pub struct FBVLPMINWIDTH_R(crate::FieldReader<u16, u16>);
39impl FBVLPMINWIDTH_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: u16) -> Self {
42        FBVLPMINWIDTH_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for FBVLPMINWIDTH_R {
46    type Target = crate::FieldReader<u16, u16>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `FBVLPMinWidth` writer - For FB, it required additional IDLE Cylcle from turning off power gates (Power is ON) to ready for normal operation. This is used to defined the # of the IDLE cycles (base on C01 Clock). According to FB spec, it will require 10uS. But for final spec, it should be from FB design team."]
53pub struct FBVLPMINWIDTH_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> FBVLPMINWIDTH_W<'a> {
57    #[doc = r"Writes raw bits to the field"]
58    #[inline(always)]
59    pub unsafe fn bits(self, value: u16) -> &'a mut W {
60        self.w.bits = (self.w.bits & !0x03ff) | (value as u32 & 0x03ff);
61        self.w
62    }
63}
64impl R {
65    #[doc = "Bits 0:9 - For FB, it required additional IDLE Cylcle from turning off power gates (Power is ON) to ready for normal operation. This is used to defined the # of the IDLE cycles (base on C01 Clock). According to FB spec, it will require 10uS. But for final spec, it should be from FB design team."]
66    #[inline(always)]
67    pub fn fbvlpmin_width(&self) -> FBVLPMINWIDTH_R {
68        FBVLPMINWIDTH_R::new((self.bits & 0x03ff) as u16)
69    }
70}
71impl W {
72    #[doc = "Bits 0:9 - For FB, it required additional IDLE Cylcle from turning off power gates (Power is ON) to ready for normal operation. This is used to defined the # of the IDLE cycles (base on C01 Clock). According to FB spec, it will require 10uS. But for final spec, it should be from FB design team."]
73    #[inline(always)]
74    pub fn fbvlpmin_width(&mut self) -> FBVLPMINWIDTH_W {
75        FBVLPMINWIDTH_W { w: self }
76    }
77    #[doc = "Writes raw bits to the register."]
78    #[inline(always)]
79    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
80        self.0.bits(bits);
81        self
82    }
83}
84#[doc = "Configuration for the amount of IDLE cycles before powering on the FB domain\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [fbvlpmin_width](index.html) module"]
85pub struct FBVLPMINWIDTH_SPEC;
86impl crate::RegisterSpec for FBVLPMINWIDTH_SPEC {
87    type Ux = u32;
88}
89#[doc = "`read()` method returns [fbvlpmin_width::R](R) reader structure"]
90impl crate::Readable for FBVLPMINWIDTH_SPEC {
91    type Reader = R;
92}
93#[doc = "`write(|w| ..)` method takes [fbvlpmin_width::W](W) writer structure"]
94impl crate::Writable for FBVLPMINWIDTH_SPEC {
95    type Writer = W;
96}
97#[doc = "`reset()` method sets FBVLPMinWidth to value 0"]
98impl crate::Resettable for FBVLPMINWIDTH_SPEC {
99    #[inline(always)]
100    fn reset_value() -> Self::Ux {
101        0
102    }
103}
eos_s3/pmu/fbvlpmin_width.rs

eos_s3/pmu/
fbvlpmin_width.rs
