eos_s3/intr_ctrl/
other_intr_en_m4.rs

1#[doc = "Register `OTHER_INTR_EN_M4` reader"]
2pub struct R(crate::R<OTHER_INTR_EN_M4_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<OTHER_INTR_EN_M4_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<OTHER_INTR_EN_M4_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<OTHER_INTR_EN_M4_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `OTHER_INTR_EN_M4` writer"]
17pub struct W(crate::W<OTHER_INTR_EN_M4_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<OTHER_INTR_EN_M4_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<OTHER_INTR_EN_M4_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<OTHER_INTR_EN_M4_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "M4 SRAM (access during low power) interrupt enable for M4\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum M4_SRAM_INTR_EN_M4_A {
40    #[doc = "0: Disable the interrupt for the power domain"]
41    ENABLE = 0,
42    #[doc = "1: Enable the interrupt for the power domain"]
43    DISABLE = 1,
44}
45impl From<M4_SRAM_INTR_EN_M4_A> for bool {
46    #[inline(always)]
47    fn from(variant: M4_SRAM_INTR_EN_M4_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `M4_SRAM_INTR_EN_M4` reader - M4 SRAM (access during low power) interrupt enable for M4"]
52pub struct M4_SRAM_INTR_EN_M4_R(crate::FieldReader<bool, M4_SRAM_INTR_EN_M4_A>);
53impl M4_SRAM_INTR_EN_M4_R {
54    #[inline(always)]
55    pub(crate) fn new(bits: bool) -> Self {
56        M4_SRAM_INTR_EN_M4_R(crate::FieldReader::new(bits))
57    }
58    #[doc = r"Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> M4_SRAM_INTR_EN_M4_A {
61        match self.bits {
62            false => M4_SRAM_INTR_EN_M4_A::ENABLE,
63            true => M4_SRAM_INTR_EN_M4_A::DISABLE,
64        }
65    }
66    #[doc = "Checks if the value of the field is `ENABLE`"]
67    #[inline(always)]
68    pub fn is_enable(&self) -> bool {
69        **self == M4_SRAM_INTR_EN_M4_A::ENABLE
70    }
71    #[doc = "Checks if the value of the field is `DISABLE`"]
72    #[inline(always)]
73    pub fn is_disable(&self) -> bool {
74        **self == M4_SRAM_INTR_EN_M4_A::DISABLE
75    }
76}
77impl core::ops::Deref for M4_SRAM_INTR_EN_M4_R {
78    type Target = crate::FieldReader<bool, M4_SRAM_INTR_EN_M4_A>;
79    #[inline(always)]
80    fn deref(&self) -> &Self::Target {
81        &self.0
82    }
83}
84#[doc = "Field `M4_SRAM_INTR_EN_M4` writer - M4 SRAM (access during low power) interrupt enable for M4"]
85pub struct M4_SRAM_INTR_EN_M4_W<'a> {
86    w: &'a mut W,
87}
88impl<'a> M4_SRAM_INTR_EN_M4_W<'a> {
89    #[doc = r"Writes `variant` to the field"]
90    #[inline(always)]
91    pub fn variant(self, variant: M4_SRAM_INTR_EN_M4_A) -> &'a mut W {
92        self.bit(variant.into())
93    }
94    #[doc = "Disable the interrupt for the power domain"]
95    #[inline(always)]
96    pub fn enable(self) -> &'a mut W {
97        self.variant(M4_SRAM_INTR_EN_M4_A::ENABLE)
98    }
99    #[doc = "Enable the interrupt for the power domain"]
100    #[inline(always)]
101    pub fn disable(self) -> &'a mut W {
102        self.variant(M4_SRAM_INTR_EN_M4_A::DISABLE)
103    }
104    #[doc = r"Sets the field bit"]
105    #[inline(always)]
106    pub fn set_bit(self) -> &'a mut W {
107        self.bit(true)
108    }
109    #[doc = r"Clears the field bit"]
110    #[inline(always)]
111    pub fn clear_bit(self) -> &'a mut W {
112        self.bit(false)
113    }
114    #[doc = r"Writes raw bits to the field"]
115    #[inline(always)]
116    pub fn bit(self, value: bool) -> &'a mut W {
117        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
118        self.w
119    }
120}
121#[doc = "UART interrupt enable for M4"]
122pub type UART_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
123#[doc = "Field `UART_INTR_EN_M4` reader - UART interrupt enable for M4"]
124pub type UART_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
125#[doc = "Field `UART_INTR_EN_M4` writer - UART interrupt enable for M4"]
126pub struct UART_INTR_EN_M4_W<'a> {
127    w: &'a mut W,
128}
129impl<'a> UART_INTR_EN_M4_W<'a> {
130    #[doc = r"Writes `variant` to the field"]
131    #[inline(always)]
132    pub fn variant(self, variant: UART_INTR_EN_M4_A) -> &'a mut W {
133        self.bit(variant.into())
134    }
135    #[doc = "Disable the interrupt for the power domain"]
136    #[inline(always)]
137    pub fn enable(self) -> &'a mut W {
138        self.variant(UART_INTR_EN_M4_A::ENABLE)
139    }
140    #[doc = "Enable the interrupt for the power domain"]
141    #[inline(always)]
142    pub fn disable(self) -> &'a mut W {
143        self.variant(UART_INTR_EN_M4_A::DISABLE)
144    }
145    #[doc = r"Sets the field bit"]
146    #[inline(always)]
147    pub fn set_bit(self) -> &'a mut W {
148        self.bit(true)
149    }
150    #[doc = r"Clears the field bit"]
151    #[inline(always)]
152    pub fn clear_bit(self) -> &'a mut W {
153        self.bit(false)
154    }
155    #[doc = r"Writes raw bits to the field"]
156    #[inline(always)]
157    pub fn bit(self, value: bool) -> &'a mut W {
158        self.w.bits =
159            (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
160        self.w
161    }
162}
163#[doc = "Timer interrupt enable for M4"]
164pub type TIMER_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
165#[doc = "Field `TIMER_INTR_EN_M4` reader - Timer interrupt enable for M4"]
166pub type TIMER_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
167#[doc = "Field `TIMER_INTR_EN_M4` writer - Timer interrupt enable for M4"]
168pub struct TIMER_INTR_EN_M4_W<'a> {
169    w: &'a mut W,
170}
171impl<'a> TIMER_INTR_EN_M4_W<'a> {
172    #[doc = r"Writes `variant` to the field"]
173    #[inline(always)]
174    pub fn variant(self, variant: TIMER_INTR_EN_M4_A) -> &'a mut W {
175        self.bit(variant.into())
176    }
177    #[doc = "Disable the interrupt for the power domain"]
178    #[inline(always)]
179    pub fn enable(self) -> &'a mut W {
180        self.variant(TIMER_INTR_EN_M4_A::ENABLE)
181    }
182    #[doc = "Enable the interrupt for the power domain"]
183    #[inline(always)]
184    pub fn disable(self) -> &'a mut W {
185        self.variant(TIMER_INTR_EN_M4_A::DISABLE)
186    }
187    #[doc = r"Sets the field bit"]
188    #[inline(always)]
189    pub fn set_bit(self) -> &'a mut W {
190        self.bit(true)
191    }
192    #[doc = r"Clears the field bit"]
193    #[inline(always)]
194    pub fn clear_bit(self) -> &'a mut W {
195        self.bit(false)
196    }
197    #[doc = r"Writes raw bits to the field"]
198    #[inline(always)]
199    pub fn bit(self, value: bool) -> &'a mut W {
200        self.w.bits =
201            (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
202        self.w
203    }
204}
205#[doc = "WDOG M4 interrupt enable for M4"]
206pub type WDOG_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
207#[doc = "Field `WDOG_INTR_EN_M4` reader - WDOG M4 interrupt enable for M4"]
208pub type WDOG_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
209#[doc = "Field `WDOG_INTR_EN_M4` writer - WDOG M4 interrupt enable for M4"]
210pub struct WDOG_INTR_EN_M4_W<'a> {
211    w: &'a mut W,
212}
213impl<'a> WDOG_INTR_EN_M4_W<'a> {
214    #[doc = r"Writes `variant` to the field"]
215    #[inline(always)]
216    pub fn variant(self, variant: WDOG_INTR_EN_M4_A) -> &'a mut W {
217        self.bit(variant.into())
218    }
219    #[doc = "Disable the interrupt for the power domain"]
220    #[inline(always)]
221    pub fn enable(self) -> &'a mut W {
222        self.variant(WDOG_INTR_EN_M4_A::ENABLE)
223    }
224    #[doc = "Enable the interrupt for the power domain"]
225    #[inline(always)]
226    pub fn disable(self) -> &'a mut W {
227        self.variant(WDOG_INTR_EN_M4_A::DISABLE)
228    }
229    #[doc = r"Sets the field bit"]
230    #[inline(always)]
231    pub fn set_bit(self) -> &'a mut W {
232        self.bit(true)
233    }
234    #[doc = r"Clears the field bit"]
235    #[inline(always)]
236    pub fn clear_bit(self) -> &'a mut W {
237        self.bit(false)
238    }
239    #[doc = r"Writes raw bits to the field"]
240    #[inline(always)]
241    pub fn bit(self, value: bool) -> &'a mut W {
242        self.w.bits =
243            (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
244        self.w
245    }
246}
247#[doc = "WDOG M4 Reset interrupt enable for M4"]
248pub type WDOG_RST_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
249#[doc = "Field `WDOG_RST_EN_M4` reader - WDOG M4 Reset interrupt enable for M4"]
250pub type WDOG_RST_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
251#[doc = "Field `WDOG_RST_EN_M4` writer - WDOG M4 Reset interrupt enable for M4"]
252pub struct WDOG_RST_EN_M4_W<'a> {
253    w: &'a mut W,
254}
255impl<'a> WDOG_RST_EN_M4_W<'a> {
256    #[doc = r"Writes `variant` to the field"]
257    #[inline(always)]
258    pub fn variant(self, variant: WDOG_RST_EN_M4_A) -> &'a mut W {
259        self.bit(variant.into())
260    }
261    #[doc = "Disable the interrupt for the power domain"]
262    #[inline(always)]
263    pub fn enable(self) -> &'a mut W {
264        self.variant(WDOG_RST_EN_M4_A::ENABLE)
265    }
266    #[doc = "Enable the interrupt for the power domain"]
267    #[inline(always)]
268    pub fn disable(self) -> &'a mut W {
269        self.variant(WDOG_RST_EN_M4_A::DISABLE)
270    }
271    #[doc = r"Sets the field bit"]
272    #[inline(always)]
273    pub fn set_bit(self) -> &'a mut W {
274        self.bit(true)
275    }
276    #[doc = r"Clears the field bit"]
277    #[inline(always)]
278    pub fn clear_bit(self) -> &'a mut W {
279        self.bit(false)
280    }
281    #[doc = r"Writes raw bits to the field"]
282    #[inline(always)]
283    pub fn bit(self, value: bool) -> &'a mut W {
284        self.w.bits =
285            (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
286        self.w
287    }
288}
289#[doc = "bus timeout interrupt enable for M4"]
290pub type TIMEOUT_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
291#[doc = "Field `TIMEOUT_INTR_EN_M4` reader - bus timeout interrupt enable for M4"]
292pub type TIMEOUT_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
293#[doc = "Field `TIMEOUT_INTR_EN_M4` writer - bus timeout interrupt enable for M4"]
294pub struct TIMEOUT_INTR_EN_M4_W<'a> {
295    w: &'a mut W,
296}
297impl<'a> TIMEOUT_INTR_EN_M4_W<'a> {
298    #[doc = r"Writes `variant` to the field"]
299    #[inline(always)]
300    pub fn variant(self, variant: TIMEOUT_INTR_EN_M4_A) -> &'a mut W {
301        self.bit(variant.into())
302    }
303    #[doc = "Disable the interrupt for the power domain"]
304    #[inline(always)]
305    pub fn enable(self) -> &'a mut W {
306        self.variant(TIMEOUT_INTR_EN_M4_A::ENABLE)
307    }
308    #[doc = "Enable the interrupt for the power domain"]
309    #[inline(always)]
310    pub fn disable(self) -> &'a mut W {
311        self.variant(TIMEOUT_INTR_EN_M4_A::DISABLE)
312    }
313    #[doc = r"Sets the field bit"]
314    #[inline(always)]
315    pub fn set_bit(self) -> &'a mut W {
316        self.bit(true)
317    }
318    #[doc = r"Clears the field bit"]
319    #[inline(always)]
320    pub fn clear_bit(self) -> &'a mut W {
321        self.bit(false)
322    }
323    #[doc = r"Writes raw bits to the field"]
324    #[inline(always)]
325    pub fn bit(self, value: bool) -> &'a mut W {
326        self.w.bits =
327            (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
328        self.w
329    }
330}
331#[doc = "M4 FPU interrupt enable for M4"]
332pub type FPU_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
333#[doc = "Field `FPU_INTR_EN_M4` reader - M4 FPU interrupt enable for M4"]
334pub type FPU_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
335#[doc = "Field `FPU_INTR_EN_M4` writer - M4 FPU interrupt enable for M4"]
336pub struct FPU_INTR_EN_M4_W<'a> {
337    w: &'a mut W,
338}
339impl<'a> FPU_INTR_EN_M4_W<'a> {
340    #[doc = r"Writes `variant` to the field"]
341    #[inline(always)]
342    pub fn variant(self, variant: FPU_INTR_EN_M4_A) -> &'a mut W {
343        self.bit(variant.into())
344    }
345    #[doc = "Disable the interrupt for the power domain"]
346    #[inline(always)]
347    pub fn enable(self) -> &'a mut W {
348        self.variant(FPU_INTR_EN_M4_A::ENABLE)
349    }
350    #[doc = "Enable the interrupt for the power domain"]
351    #[inline(always)]
352    pub fn disable(self) -> &'a mut W {
353        self.variant(FPU_INTR_EN_M4_A::DISABLE)
354    }
355    #[doc = r"Sets the field bit"]
356    #[inline(always)]
357    pub fn set_bit(self) -> &'a mut W {
358        self.bit(true)
359    }
360    #[doc = r"Clears the field bit"]
361    #[inline(always)]
362    pub fn clear_bit(self) -> &'a mut W {
363        self.bit(false)
364    }
365    #[doc = r"Writes raw bits to the field"]
366    #[inline(always)]
367    pub fn bit(self, value: bool) -> &'a mut W {
368        self.w.bits =
369            (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
370        self.w
371    }
372}
373#[doc = "Packet FIFO Bank interrupt enable for M4"]
374pub type PKFB_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
375#[doc = "Field `PKFB_INTR_EN_M4` reader - Packet FIFO Bank interrupt enable for M4"]
376pub type PKFB_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
377#[doc = "Field `PKFB_INTR_EN_M4` writer - Packet FIFO Bank interrupt enable for M4"]
378pub struct PKFB_INTR_EN_M4_W<'a> {
379    w: &'a mut W,
380}
381impl<'a> PKFB_INTR_EN_M4_W<'a> {
382    #[doc = r"Writes `variant` to the field"]
383    #[inline(always)]
384    pub fn variant(self, variant: PKFB_INTR_EN_M4_A) -> &'a mut W {
385        self.bit(variant.into())
386    }
387    #[doc = "Disable the interrupt for the power domain"]
388    #[inline(always)]
389    pub fn enable(self) -> &'a mut W {
390        self.variant(PKFB_INTR_EN_M4_A::ENABLE)
391    }
392    #[doc = "Enable the interrupt for the power domain"]
393    #[inline(always)]
394    pub fn disable(self) -> &'a mut W {
395        self.variant(PKFB_INTR_EN_M4_A::DISABLE)
396    }
397    #[doc = r"Sets the field bit"]
398    #[inline(always)]
399    pub fn set_bit(self) -> &'a mut W {
400        self.bit(true)
401    }
402    #[doc = r"Clears the field bit"]
403    #[inline(always)]
404    pub fn clear_bit(self) -> &'a mut W {
405        self.bit(false)
406    }
407    #[doc = r"Writes raw bits to the field"]
408    #[inline(always)]
409    pub fn bit(self, value: bool) -> &'a mut W {
410        self.w.bits =
411            (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
412        self.w
413    }
414}
415#[doc = "SPI Master interrupt enable for M4"]
416pub type SPI_MS_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
417#[doc = "Field `SPI_MS_INTR_EN_M4` reader - SPI Master interrupt enable for M4"]
418pub type SPI_MS_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
419#[doc = "Field `SPI_MS_INTR_EN_M4` writer - SPI Master interrupt enable for M4"]
420pub struct SPI_MS_INTR_EN_M4_W<'a> {
421    w: &'a mut W,
422}
423impl<'a> SPI_MS_INTR_EN_M4_W<'a> {
424    #[doc = r"Writes `variant` to the field"]
425    #[inline(always)]
426    pub fn variant(self, variant: SPI_MS_INTR_EN_M4_A) -> &'a mut W {
427        self.bit(variant.into())
428    }
429    #[doc = "Disable the interrupt for the power domain"]
430    #[inline(always)]
431    pub fn enable(self) -> &'a mut W {
432        self.variant(SPI_MS_INTR_EN_M4_A::ENABLE)
433    }
434    #[doc = "Enable the interrupt for the power domain"]
435    #[inline(always)]
436    pub fn disable(self) -> &'a mut W {
437        self.variant(SPI_MS_INTR_EN_M4_A::DISABLE)
438    }
439    #[doc = r"Sets the field bit"]
440    #[inline(always)]
441    pub fn set_bit(self) -> &'a mut W {
442        self.bit(true)
443    }
444    #[doc = r"Clears the field bit"]
445    #[inline(always)]
446    pub fn clear_bit(self) -> &'a mut W {
447        self.bit(false)
448    }
449    #[doc = r"Writes raw bits to the field"]
450    #[inline(always)]
451    pub fn bit(self, value: bool) -> &'a mut W {
452        self.w.bits =
453            (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
454        self.w
455    }
456}
457#[doc = "Config DMA interrupt enable for M4"]
458pub type CFG_DMA_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
459#[doc = "Field `CFG_DMA_INTR_EN_M4` reader - Config DMA interrupt enable for M4"]
460pub type CFG_DMA_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
461#[doc = "Field `CFG_DMA_INTR_EN_M4` writer - Config DMA interrupt enable for M4"]
462pub struct CFG_DMA_INTR_EN_M4_W<'a> {
463    w: &'a mut W,
464}
465impl<'a> CFG_DMA_INTR_EN_M4_W<'a> {
466    #[doc = r"Writes `variant` to the field"]
467    #[inline(always)]
468    pub fn variant(self, variant: CFG_DMA_INTR_EN_M4_A) -> &'a mut W {
469        self.bit(variant.into())
470    }
471    #[doc = "Disable the interrupt for the power domain"]
472    #[inline(always)]
473    pub fn enable(self) -> &'a mut W {
474        self.variant(CFG_DMA_INTR_EN_M4_A::ENABLE)
475    }
476    #[doc = "Enable the interrupt for the power domain"]
477    #[inline(always)]
478    pub fn disable(self) -> &'a mut W {
479        self.variant(CFG_DMA_INTR_EN_M4_A::DISABLE)
480    }
481    #[doc = r"Sets the field bit"]
482    #[inline(always)]
483    pub fn set_bit(self) -> &'a mut W {
484        self.bit(true)
485    }
486    #[doc = r"Clears the field bit"]
487    #[inline(always)]
488    pub fn clear_bit(self) -> &'a mut W {
489        self.bit(false)
490    }
491    #[doc = r"Writes raw bits to the field"]
492    #[inline(always)]
493    pub fn bit(self, value: bool) -> &'a mut W {
494        self.w.bits =
495            (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
496        self.w
497    }
498}
499#[doc = "PMU Timer interrupt enable for M4"]
500pub type PMU_TMR_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
501#[doc = "Field `PMU_TMR_INTR_EN_M4` reader - PMU Timer interrupt enable for M4"]
502pub type PMU_TMR_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
503#[doc = "Field `PMU_TMR_INTR_EN_M4` writer - PMU Timer interrupt enable for M4"]
504pub struct PMU_TMR_INTR_EN_M4_W<'a> {
505    w: &'a mut W,
506}
507impl<'a> PMU_TMR_INTR_EN_M4_W<'a> {
508    #[doc = r"Writes `variant` to the field"]
509    #[inline(always)]
510    pub fn variant(self, variant: PMU_TMR_INTR_EN_M4_A) -> &'a mut W {
511        self.bit(variant.into())
512    }
513    #[doc = "Disable the interrupt for the power domain"]
514    #[inline(always)]
515    pub fn enable(self) -> &'a mut W {
516        self.variant(PMU_TMR_INTR_EN_M4_A::ENABLE)
517    }
518    #[doc = "Enable the interrupt for the power domain"]
519    #[inline(always)]
520    pub fn disable(self) -> &'a mut W {
521        self.variant(PMU_TMR_INTR_EN_M4_A::DISABLE)
522    }
523    #[doc = r"Sets the field bit"]
524    #[inline(always)]
525    pub fn set_bit(self) -> &'a mut W {
526        self.bit(true)
527    }
528    #[doc = r"Clears the field bit"]
529    #[inline(always)]
530    pub fn clear_bit(self) -> &'a mut W {
531        self.bit(false)
532    }
533    #[doc = r"Writes raw bits to the field"]
534    #[inline(always)]
535    pub fn bit(self, value: bool) -> &'a mut W {
536        self.w.bits =
537            (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
538        self.w
539    }
540}
541#[doc = "ADC interrupt enable for M4"]
542pub type ADC_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
543#[doc = "Field `ADC_INTR_EN_M4` reader - ADC interrupt enable for M4"]
544pub type ADC_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
545#[doc = "Field `ADC_INTR_EN_M4` writer - ADC interrupt enable for M4"]
546pub struct ADC_INTR_EN_M4_W<'a> {
547    w: &'a mut W,
548}
549impl<'a> ADC_INTR_EN_M4_W<'a> {
550    #[doc = r"Writes `variant` to the field"]
551    #[inline(always)]
552    pub fn variant(self, variant: ADC_INTR_EN_M4_A) -> &'a mut W {
553        self.bit(variant.into())
554    }
555    #[doc = "Disable the interrupt for the power domain"]
556    #[inline(always)]
557    pub fn enable(self) -> &'a mut W {
558        self.variant(ADC_INTR_EN_M4_A::ENABLE)
559    }
560    #[doc = "Enable the interrupt for the power domain"]
561    #[inline(always)]
562    pub fn disable(self) -> &'a mut W {
563        self.variant(ADC_INTR_EN_M4_A::DISABLE)
564    }
565    #[doc = r"Sets the field bit"]
566    #[inline(always)]
567    pub fn set_bit(self) -> &'a mut W {
568        self.bit(true)
569    }
570    #[doc = r"Clears the field bit"]
571    #[inline(always)]
572    pub fn clear_bit(self) -> &'a mut W {
573        self.bit(false)
574    }
575    #[doc = r"Writes raw bits to the field"]
576    #[inline(always)]
577    pub fn bit(self, value: bool) -> &'a mut W {
578        self.w.bits =
579            (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
580        self.w
581    }
582}
583#[doc = "RTC interrupt enable for M4"]
584pub type RTC_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
585#[doc = "Field `RTC_INTR_EN_M4` reader - RTC interrupt enable for M4"]
586pub type RTC_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
587#[doc = "Field `RTC_INTR_EN_M4` writer - RTC interrupt enable for M4"]
588pub struct RTC_INTR_EN_M4_W<'a> {
589    w: &'a mut W,
590}
591impl<'a> RTC_INTR_EN_M4_W<'a> {
592    #[doc = r"Writes `variant` to the field"]
593    #[inline(always)]
594    pub fn variant(self, variant: RTC_INTR_EN_M4_A) -> &'a mut W {
595        self.bit(variant.into())
596    }
597    #[doc = "Disable the interrupt for the power domain"]
598    #[inline(always)]
599    pub fn enable(self) -> &'a mut W {
600        self.variant(RTC_INTR_EN_M4_A::ENABLE)
601    }
602    #[doc = "Enable the interrupt for the power domain"]
603    #[inline(always)]
604    pub fn disable(self) -> &'a mut W {
605        self.variant(RTC_INTR_EN_M4_A::DISABLE)
606    }
607    #[doc = r"Sets the field bit"]
608    #[inline(always)]
609    pub fn set_bit(self) -> &'a mut W {
610        self.bit(true)
611    }
612    #[doc = r"Clears the field bit"]
613    #[inline(always)]
614    pub fn clear_bit(self) -> &'a mut W {
615        self.bit(false)
616    }
617    #[doc = r"Writes raw bits to the field"]
618    #[inline(always)]
619    pub fn bit(self, value: bool) -> &'a mut W {
620        self.w.bits =
621            (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
622        self.w
623    }
624}
625#[doc = "Reset interrupt enable for M4"]
626pub type RST_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
627#[doc = "Field `RST_INTR_EN_M4` reader - Reset interrupt enable for M4"]
628pub type RST_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
629#[doc = "Field `RST_INTR_EN_M4` writer - Reset interrupt enable for M4"]
630pub struct RST_INTR_EN_M4_W<'a> {
631    w: &'a mut W,
632}
633impl<'a> RST_INTR_EN_M4_W<'a> {
634    #[doc = r"Writes `variant` to the field"]
635    #[inline(always)]
636    pub fn variant(self, variant: RST_INTR_EN_M4_A) -> &'a mut W {
637        self.bit(variant.into())
638    }
639    #[doc = "Disable the interrupt for the power domain"]
640    #[inline(always)]
641    pub fn enable(self) -> &'a mut W {
642        self.variant(RST_INTR_EN_M4_A::ENABLE)
643    }
644    #[doc = "Enable the interrupt for the power domain"]
645    #[inline(always)]
646    pub fn disable(self) -> &'a mut W {
647        self.variant(RST_INTR_EN_M4_A::DISABLE)
648    }
649    #[doc = r"Sets the field bit"]
650    #[inline(always)]
651    pub fn set_bit(self) -> &'a mut W {
652        self.bit(true)
653    }
654    #[doc = r"Clears the field bit"]
655    #[inline(always)]
656    pub fn clear_bit(self) -> &'a mut W {
657        self.bit(false)
658    }
659    #[doc = r"Writes raw bits to the field"]
660    #[inline(always)]
661    pub fn bit(self, value: bool) -> &'a mut W {
662        self.w.bits =
663            (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
664        self.w
665    }
666}
667#[doc = "FFE0 other interrupts enable for M4"]
668pub type FFE0_INTR_OTHERS_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
669#[doc = "Field `FFE0_INTR_OTHERS_EN_M4` reader - FFE0 other interrupts enable for M4"]
670pub type FFE0_INTR_OTHERS_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
671#[doc = "Field `FFE0_INTR_OTHERS_EN_M4` writer - FFE0 other interrupts enable for M4"]
672pub struct FFE0_INTR_OTHERS_EN_M4_W<'a> {
673    w: &'a mut W,
674}
675impl<'a> FFE0_INTR_OTHERS_EN_M4_W<'a> {
676    #[doc = r"Writes `variant` to the field"]
677    #[inline(always)]
678    pub fn variant(self, variant: FFE0_INTR_OTHERS_EN_M4_A) -> &'a mut W {
679        self.bit(variant.into())
680    }
681    #[doc = "Disable the interrupt for the power domain"]
682    #[inline(always)]
683    pub fn enable(self) -> &'a mut W {
684        self.variant(FFE0_INTR_OTHERS_EN_M4_A::ENABLE)
685    }
686    #[doc = "Enable the interrupt for the power domain"]
687    #[inline(always)]
688    pub fn disable(self) -> &'a mut W {
689        self.variant(FFE0_INTR_OTHERS_EN_M4_A::DISABLE)
690    }
691    #[doc = r"Sets the field bit"]
692    #[inline(always)]
693    pub fn set_bit(self) -> &'a mut W {
694        self.bit(true)
695    }
696    #[doc = r"Clears the field bit"]
697    #[inline(always)]
698    pub fn clear_bit(self) -> &'a mut W {
699        self.bit(false)
700    }
701    #[doc = r"Writes raw bits to the field"]
702    #[inline(always)]
703    pub fn bit(self, value: bool) -> &'a mut W {
704        self.w.bits =
705            (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
706        self.w
707    }
708}
709#[doc = "AP Boot interrupt enable for M4"]
710pub type APBOOT_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
711#[doc = "Field `APBOOT_INTR_EN_M4` reader - AP Boot interrupt enable for M4"]
712pub type APBOOT_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
713#[doc = "Field `APBOOT_INTR_EN_M4` writer - AP Boot interrupt enable for M4"]
714pub struct APBOOT_INTR_EN_M4_W<'a> {
715    w: &'a mut W,
716}
717impl<'a> APBOOT_INTR_EN_M4_W<'a> {
718    #[doc = r"Writes `variant` to the field"]
719    #[inline(always)]
720    pub fn variant(self, variant: APBOOT_INTR_EN_M4_A) -> &'a mut W {
721        self.bit(variant.into())
722    }
723    #[doc = "Disable the interrupt for the power domain"]
724    #[inline(always)]
725    pub fn enable(self) -> &'a mut W {
726        self.variant(APBOOT_INTR_EN_M4_A::ENABLE)
727    }
728    #[doc = "Enable the interrupt for the power domain"]
729    #[inline(always)]
730    pub fn disable(self) -> &'a mut W {
731        self.variant(APBOOT_INTR_EN_M4_A::DISABLE)
732    }
733    #[doc = r"Sets the field bit"]
734    #[inline(always)]
735    pub fn set_bit(self) -> &'a mut W {
736        self.bit(true)
737    }
738    #[doc = r"Clears the field bit"]
739    #[inline(always)]
740    pub fn clear_bit(self) -> &'a mut W {
741        self.bit(false)
742    }
743    #[doc = r"Writes raw bits to the field"]
744    #[inline(always)]
745    pub fn bit(self, value: bool) -> &'a mut W {
746        self.w.bits =
747            (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
748        self.w
749    }
750}
751#[doc = "Absence of LDO30 power good interrupt enable for M4"]
752pub type LDO30_PG_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
753#[doc = "Field `LDO30_PG_INTR_EN_M4` reader - Absence of LDO30 power good interrupt enable for M4"]
754pub type LDO30_PG_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
755#[doc = "Field `LDO30_PG_INTR_EN_M4` writer - Absence of LDO30 power good interrupt enable for M4"]
756pub struct LDO30_PG_INTR_EN_M4_W<'a> {
757    w: &'a mut W,
758}
759impl<'a> LDO30_PG_INTR_EN_M4_W<'a> {
760    #[doc = r"Writes `variant` to the field"]
761    #[inline(always)]
762    pub fn variant(self, variant: LDO30_PG_INTR_EN_M4_A) -> &'a mut W {
763        self.bit(variant.into())
764    }
765    #[doc = "Disable the interrupt for the power domain"]
766    #[inline(always)]
767    pub fn enable(self) -> &'a mut W {
768        self.variant(LDO30_PG_INTR_EN_M4_A::ENABLE)
769    }
770    #[doc = "Enable the interrupt for the power domain"]
771    #[inline(always)]
772    pub fn disable(self) -> &'a mut W {
773        self.variant(LDO30_PG_INTR_EN_M4_A::DISABLE)
774    }
775    #[doc = r"Sets the field bit"]
776    #[inline(always)]
777    pub fn set_bit(self) -> &'a mut W {
778        self.bit(true)
779    }
780    #[doc = r"Clears the field bit"]
781    #[inline(always)]
782    pub fn clear_bit(self) -> &'a mut W {
783        self.bit(false)
784    }
785    #[doc = r"Writes raw bits to the field"]
786    #[inline(always)]
787    pub fn bit(self, value: bool) -> &'a mut W {
788        self.w.bits =
789            (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
790        self.w
791    }
792}
793#[doc = "Absence of LDO50 power good interrupt enable for M4"]
794pub type LDO50_PG_INTR_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
795#[doc = "Field `LDO50_PG_INTR_EN_M4` reader - Absence of LDO50 power good interrupt enable for M4"]
796pub type LDO50_PG_INTR_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
797#[doc = "Field `LDO50_PG_INTR_EN_M4` writer - Absence of LDO50 power good interrupt enable for M4"]
798pub struct LDO50_PG_INTR_EN_M4_W<'a> {
799    w: &'a mut W,
800}
801impl<'a> LDO50_PG_INTR_EN_M4_W<'a> {
802    #[doc = r"Writes `variant` to the field"]
803    #[inline(always)]
804    pub fn variant(self, variant: LDO50_PG_INTR_EN_M4_A) -> &'a mut W {
805        self.bit(variant.into())
806    }
807    #[doc = "Disable the interrupt for the power domain"]
808    #[inline(always)]
809    pub fn enable(self) -> &'a mut W {
810        self.variant(LDO50_PG_INTR_EN_M4_A::ENABLE)
811    }
812    #[doc = "Enable the interrupt for the power domain"]
813    #[inline(always)]
814    pub fn disable(self) -> &'a mut W {
815        self.variant(LDO50_PG_INTR_EN_M4_A::DISABLE)
816    }
817    #[doc = r"Sets the field bit"]
818    #[inline(always)]
819    pub fn set_bit(self) -> &'a mut W {
820        self.bit(true)
821    }
822    #[doc = r"Clears the field bit"]
823    #[inline(always)]
824    pub fn clear_bit(self) -> &'a mut W {
825        self.bit(false)
826    }
827    #[doc = r"Writes raw bits to the field"]
828    #[inline(always)]
829    pub fn bit(self, value: bool) -> &'a mut W {
830        self.w.bits =
831            (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
832        self.w
833    }
834}
835#[doc = "LPSD Voice detected interrupt enable for M4"]
836pub type LPSD_VOICE_DET_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
837#[doc = "Field `LPSD_VOICE_DET_EN_M4` reader - LPSD Voice detected interrupt enable for M4"]
838pub type LPSD_VOICE_DET_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
839#[doc = "Field `LPSD_VOICE_DET_EN_M4` writer - LPSD Voice detected interrupt enable for M4"]
840pub struct LPSD_VOICE_DET_EN_M4_W<'a> {
841    w: &'a mut W,
842}
843impl<'a> LPSD_VOICE_DET_EN_M4_W<'a> {
844    #[doc = r"Writes `variant` to the field"]
845    #[inline(always)]
846    pub fn variant(self, variant: LPSD_VOICE_DET_EN_M4_A) -> &'a mut W {
847        self.bit(variant.into())
848    }
849    #[doc = "Disable the interrupt for the power domain"]
850    #[inline(always)]
851    pub fn enable(self) -> &'a mut W {
852        self.variant(LPSD_VOICE_DET_EN_M4_A::ENABLE)
853    }
854    #[doc = "Enable the interrupt for the power domain"]
855    #[inline(always)]
856    pub fn disable(self) -> &'a mut W {
857        self.variant(LPSD_VOICE_DET_EN_M4_A::DISABLE)
858    }
859    #[doc = r"Sets the field bit"]
860    #[inline(always)]
861    pub fn set_bit(self) -> &'a mut W {
862        self.bit(true)
863    }
864    #[doc = r"Clears the field bit"]
865    #[inline(always)]
866    pub fn clear_bit(self) -> &'a mut W {
867        self.bit(false)
868    }
869    #[doc = r"Writes raw bits to the field"]
870    #[inline(always)]
871    pub fn bit(self, value: bool) -> &'a mut W {
872        self.w.bits =
873            (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
874        self.w
875    }
876}
877#[doc = "Digital Mic Voice detected interrupt enable for M4"]
878pub type DMIC_VOICE_DET_EN_M4_A = M4_SRAM_INTR_EN_M4_A;
879#[doc = "Field `DMIC_VOICE_DET_EN_M4` reader - Digital Mic Voice detected interrupt enable for M4"]
880pub type DMIC_VOICE_DET_EN_M4_R = M4_SRAM_INTR_EN_M4_R;
881#[doc = "Field `DMIC_VOICE_DET_EN_M4` writer - Digital Mic Voice detected interrupt enable for M4"]
882pub struct DMIC_VOICE_DET_EN_M4_W<'a> {
883    w: &'a mut W,
884}
885impl<'a> DMIC_VOICE_DET_EN_M4_W<'a> {
886    #[doc = r"Writes `variant` to the field"]
887    #[inline(always)]
888    pub fn variant(self, variant: DMIC_VOICE_DET_EN_M4_A) -> &'a mut W {
889        self.bit(variant.into())
890    }
891    #[doc = "Disable the interrupt for the power domain"]
892    #[inline(always)]
893    pub fn enable(self) -> &'a mut W {
894        self.variant(DMIC_VOICE_DET_EN_M4_A::ENABLE)
895    }
896    #[doc = "Enable the interrupt for the power domain"]
897    #[inline(always)]
898    pub fn disable(self) -> &'a mut W {
899        self.variant(DMIC_VOICE_DET_EN_M4_A::DISABLE)
900    }
901    #[doc = r"Sets the field bit"]
902    #[inline(always)]
903    pub fn set_bit(self) -> &'a mut W {
904        self.bit(true)
905    }
906    #[doc = r"Clears the field bit"]
907    #[inline(always)]
908    pub fn clear_bit(self) -> &'a mut W {
909        self.bit(false)
910    }
911    #[doc = r"Writes raw bits to the field"]
912    #[inline(always)]
913    pub fn bit(self, value: bool) -> &'a mut W {
914        self.w.bits =
915            (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
916        self.w
917    }
918}
919impl R {
920    #[doc = "Bit 0 - M4 SRAM (access during low power) interrupt enable for M4"]
921    #[inline(always)]
922    pub fn m4_sram_intr_en_m4(&self) -> M4_SRAM_INTR_EN_M4_R {
923        M4_SRAM_INTR_EN_M4_R::new((self.bits & 0x01) != 0)
924    }
925    #[doc = "Bit 1 - UART interrupt enable for M4"]
926    #[inline(always)]
927    pub fn uart_intr_en_m4(&self) -> UART_INTR_EN_M4_R {
928        UART_INTR_EN_M4_R::new(((self.bits >> 1) & 0x01) != 0)
929    }
930    #[doc = "Bit 2 - Timer interrupt enable for M4"]
931    #[inline(always)]
932    pub fn timer_intr_en_m4(&self) -> TIMER_INTR_EN_M4_R {
933        TIMER_INTR_EN_M4_R::new(((self.bits >> 2) & 0x01) != 0)
934    }
935    #[doc = "Bit 3 - WDOG M4 interrupt enable for M4"]
936    #[inline(always)]
937    pub fn wdog_intr_en_m4(&self) -> WDOG_INTR_EN_M4_R {
938        WDOG_INTR_EN_M4_R::new(((self.bits >> 3) & 0x01) != 0)
939    }
940    #[doc = "Bit 4 - WDOG M4 Reset interrupt enable for M4"]
941    #[inline(always)]
942    pub fn wdog_rst_en_m4(&self) -> WDOG_RST_EN_M4_R {
943        WDOG_RST_EN_M4_R::new(((self.bits >> 4) & 0x01) != 0)
944    }
945    #[doc = "Bit 5 - bus timeout interrupt enable for M4"]
946    #[inline(always)]
947    pub fn timeout_intr_en_m4(&self) -> TIMEOUT_INTR_EN_M4_R {
948        TIMEOUT_INTR_EN_M4_R::new(((self.bits >> 5) & 0x01) != 0)
949    }
950    #[doc = "Bit 6 - M4 FPU interrupt enable for M4"]
951    #[inline(always)]
952    pub fn fpu_intr_en_m4(&self) -> FPU_INTR_EN_M4_R {
953        FPU_INTR_EN_M4_R::new(((self.bits >> 6) & 0x01) != 0)
954    }
955    #[doc = "Bit 7 - Packet FIFO Bank interrupt enable for M4"]
956    #[inline(always)]
957    pub fn pkfb_intr_en_m4(&self) -> PKFB_INTR_EN_M4_R {
958        PKFB_INTR_EN_M4_R::new(((self.bits >> 7) & 0x01) != 0)
959    }
960    #[doc = "Bit 10 - SPI Master interrupt enable for M4"]
961    #[inline(always)]
962    pub fn spi_ms_intr_en_m4(&self) -> SPI_MS_INTR_EN_M4_R {
963        SPI_MS_INTR_EN_M4_R::new(((self.bits >> 10) & 0x01) != 0)
964    }
965    #[doc = "Bit 11 - Config DMA interrupt enable for M4"]
966    #[inline(always)]
967    pub fn cfg_dma_intr_en_m4(&self) -> CFG_DMA_INTR_EN_M4_R {
968        CFG_DMA_INTR_EN_M4_R::new(((self.bits >> 11) & 0x01) != 0)
969    }
970    #[doc = "Bit 12 - PMU Timer interrupt enable for M4"]
971    #[inline(always)]
972    pub fn pmu_tmr_intr_en_m4(&self) -> PMU_TMR_INTR_EN_M4_R {
973        PMU_TMR_INTR_EN_M4_R::new(((self.bits >> 12) & 0x01) != 0)
974    }
975    #[doc = "Bit 13 - ADC interrupt enable for M4"]
976    #[inline(always)]
977    pub fn adc_intr_en_m4(&self) -> ADC_INTR_EN_M4_R {
978        ADC_INTR_EN_M4_R::new(((self.bits >> 13) & 0x01) != 0)
979    }
980    #[doc = "Bit 14 - RTC interrupt enable for M4"]
981    #[inline(always)]
982    pub fn rtc_intr_en_m4(&self) -> RTC_INTR_EN_M4_R {
983        RTC_INTR_EN_M4_R::new(((self.bits >> 14) & 0x01) != 0)
984    }
985    #[doc = "Bit 15 - Reset interrupt enable for M4"]
986    #[inline(always)]
987    pub fn rst_intr_en_m4(&self) -> RST_INTR_EN_M4_R {
988        RST_INTR_EN_M4_R::new(((self.bits >> 15) & 0x01) != 0)
989    }
990    #[doc = "Bit 16 - FFE0 other interrupts enable for M4"]
991    #[inline(always)]
992    pub fn ffe0_intr_others_en_m4(&self) -> FFE0_INTR_OTHERS_EN_M4_R {
993        FFE0_INTR_OTHERS_EN_M4_R::new(((self.bits >> 16) & 0x01) != 0)
994    }
995    #[doc = "Bit 18 - AP Boot interrupt enable for M4"]
996    #[inline(always)]
997    pub fn apboot_intr_en_m4(&self) -> APBOOT_INTR_EN_M4_R {
998        APBOOT_INTR_EN_M4_R::new(((self.bits >> 18) & 0x01) != 0)
999    }
1000    #[doc = "Bit 19 - Absence of LDO30 power good interrupt enable for M4"]
1001    #[inline(always)]
1002    pub fn ldo30_pg_intr_en_m4(&self) -> LDO30_PG_INTR_EN_M4_R {
1003        LDO30_PG_INTR_EN_M4_R::new(((self.bits >> 19) & 0x01) != 0)
1004    }
1005    #[doc = "Bit 20 - Absence of LDO50 power good interrupt enable for M4"]
1006    #[inline(always)]
1007    pub fn ldo50_pg_intr_en_m4(&self) -> LDO50_PG_INTR_EN_M4_R {
1008        LDO50_PG_INTR_EN_M4_R::new(((self.bits >> 20) & 0x01) != 0)
1009    }
1010    #[doc = "Bit 22 - LPSD Voice detected interrupt enable for M4"]
1011    #[inline(always)]
1012    pub fn lpsd_voice_det_en_m4(&self) -> LPSD_VOICE_DET_EN_M4_R {
1013        LPSD_VOICE_DET_EN_M4_R::new(((self.bits >> 22) & 0x01) != 0)
1014    }
1015    #[doc = "Bit 23 - Digital Mic Voice detected interrupt enable for M4"]
1016    #[inline(always)]
1017    pub fn dmic_voice_det_en_m4(&self) -> DMIC_VOICE_DET_EN_M4_R {
1018        DMIC_VOICE_DET_EN_M4_R::new(((self.bits >> 23) & 0x01) != 0)
1019    }
1020}
1021impl W {
1022    #[doc = "Bit 0 - M4 SRAM (access during low power) interrupt enable for M4"]
1023    #[inline(always)]
1024    pub fn m4_sram_intr_en_m4(&mut self) -> M4_SRAM_INTR_EN_M4_W {
1025        M4_SRAM_INTR_EN_M4_W { w: self }
1026    }
1027    #[doc = "Bit 1 - UART interrupt enable for M4"]
1028    #[inline(always)]
1029    pub fn uart_intr_en_m4(&mut self) -> UART_INTR_EN_M4_W {
1030        UART_INTR_EN_M4_W { w: self }
1031    }
1032    #[doc = "Bit 2 - Timer interrupt enable for M4"]
1033    #[inline(always)]
1034    pub fn timer_intr_en_m4(&mut self) -> TIMER_INTR_EN_M4_W {
1035        TIMER_INTR_EN_M4_W { w: self }
1036    }
1037    #[doc = "Bit 3 - WDOG M4 interrupt enable for M4"]
1038    #[inline(always)]
1039    pub fn wdog_intr_en_m4(&mut self) -> WDOG_INTR_EN_M4_W {
1040        WDOG_INTR_EN_M4_W { w: self }
1041    }
1042    #[doc = "Bit 4 - WDOG M4 Reset interrupt enable for M4"]
1043    #[inline(always)]
1044    pub fn wdog_rst_en_m4(&mut self) -> WDOG_RST_EN_M4_W {
1045        WDOG_RST_EN_M4_W { w: self }
1046    }
1047    #[doc = "Bit 5 - bus timeout interrupt enable for M4"]
1048    #[inline(always)]
1049    pub fn timeout_intr_en_m4(&mut self) -> TIMEOUT_INTR_EN_M4_W {
1050        TIMEOUT_INTR_EN_M4_W { w: self }
1051    }
1052    #[doc = "Bit 6 - M4 FPU interrupt enable for M4"]
1053    #[inline(always)]
1054    pub fn fpu_intr_en_m4(&mut self) -> FPU_INTR_EN_M4_W {
1055        FPU_INTR_EN_M4_W { w: self }
1056    }
1057    #[doc = "Bit 7 - Packet FIFO Bank interrupt enable for M4"]
1058    #[inline(always)]
1059    pub fn pkfb_intr_en_m4(&mut self) -> PKFB_INTR_EN_M4_W {
1060        PKFB_INTR_EN_M4_W { w: self }
1061    }
1062    #[doc = "Bit 10 - SPI Master interrupt enable for M4"]
1063    #[inline(always)]
1064    pub fn spi_ms_intr_en_m4(&mut self) -> SPI_MS_INTR_EN_M4_W {
1065        SPI_MS_INTR_EN_M4_W { w: self }
1066    }
1067    #[doc = "Bit 11 - Config DMA interrupt enable for M4"]
1068    #[inline(always)]
1069    pub fn cfg_dma_intr_en_m4(&mut self) -> CFG_DMA_INTR_EN_M4_W {
1070        CFG_DMA_INTR_EN_M4_W { w: self }
1071    }
1072    #[doc = "Bit 12 - PMU Timer interrupt enable for M4"]
1073    #[inline(always)]
1074    pub fn pmu_tmr_intr_en_m4(&mut self) -> PMU_TMR_INTR_EN_M4_W {
1075        PMU_TMR_INTR_EN_M4_W { w: self }
1076    }
1077    #[doc = "Bit 13 - ADC interrupt enable for M4"]
1078    #[inline(always)]
1079    pub fn adc_intr_en_m4(&mut self) -> ADC_INTR_EN_M4_W {
1080        ADC_INTR_EN_M4_W { w: self }
1081    }
1082    #[doc = "Bit 14 - RTC interrupt enable for M4"]
1083    #[inline(always)]
1084    pub fn rtc_intr_en_m4(&mut self) -> RTC_INTR_EN_M4_W {
1085        RTC_INTR_EN_M4_W { w: self }
1086    }
1087    #[doc = "Bit 15 - Reset interrupt enable for M4"]
1088    #[inline(always)]
1089    pub fn rst_intr_en_m4(&mut self) -> RST_INTR_EN_M4_W {
1090        RST_INTR_EN_M4_W { w: self }
1091    }
1092    #[doc = "Bit 16 - FFE0 other interrupts enable for M4"]
1093    #[inline(always)]
1094    pub fn ffe0_intr_others_en_m4(&mut self) -> FFE0_INTR_OTHERS_EN_M4_W {
1095        FFE0_INTR_OTHERS_EN_M4_W { w: self }
1096    }
1097    #[doc = "Bit 18 - AP Boot interrupt enable for M4"]
1098    #[inline(always)]
1099    pub fn apboot_intr_en_m4(&mut self) -> APBOOT_INTR_EN_M4_W {
1100        APBOOT_INTR_EN_M4_W { w: self }
1101    }
1102    #[doc = "Bit 19 - Absence of LDO30 power good interrupt enable for M4"]
1103    #[inline(always)]
1104    pub fn ldo30_pg_intr_en_m4(&mut self) -> LDO30_PG_INTR_EN_M4_W {
1105        LDO30_PG_INTR_EN_M4_W { w: self }
1106    }
1107    #[doc = "Bit 20 - Absence of LDO50 power good interrupt enable for M4"]
1108    #[inline(always)]
1109    pub fn ldo50_pg_intr_en_m4(&mut self) -> LDO50_PG_INTR_EN_M4_W {
1110        LDO50_PG_INTR_EN_M4_W { w: self }
1111    }
1112    #[doc = "Bit 22 - LPSD Voice detected interrupt enable for M4"]
1113    #[inline(always)]
1114    pub fn lpsd_voice_det_en_m4(&mut self) -> LPSD_VOICE_DET_EN_M4_W {
1115        LPSD_VOICE_DET_EN_M4_W { w: self }
1116    }
1117    #[doc = "Bit 23 - Digital Mic Voice detected interrupt enable for M4"]
1118    #[inline(always)]
1119    pub fn dmic_voice_det_en_m4(&mut self) -> DMIC_VOICE_DET_EN_M4_W {
1120        DMIC_VOICE_DET_EN_M4_W { w: self }
1121    }
1122    #[doc = "Writes raw bits to the register."]
1123    #[inline(always)]
1124    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1125        self.0.bits(bits);
1126        self
1127    }
1128}
1129#[doc = "Various interrupt enable for M4\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [other_intr_en_m4](index.html) module"]
1130pub struct OTHER_INTR_EN_M4_SPEC;
1131impl crate::RegisterSpec for OTHER_INTR_EN_M4_SPEC {
1132    type Ux = u32;
1133}
1134#[doc = "`read()` method returns [other_intr_en_m4::R](R) reader structure"]
1135impl crate::Readable for OTHER_INTR_EN_M4_SPEC {
1136    type Reader = R;
1137}
1138#[doc = "`write(|w| ..)` method takes [other_intr_en_m4::W](W) writer structure"]
1139impl crate::Writable for OTHER_INTR_EN_M4_SPEC {
1140    type Writer = W;
1141}
1142#[doc = "`reset()` method sets OTHER_INTR_EN_M4 to value 0"]
1143impl crate::Resettable for OTHER_INTR_EN_M4_SPEC {
1144    #[inline(always)]
1145    fn reset_value() -> Self::Ux {
1146        0
1147    }
1148}
eos_s3/intr_ctrl/other_intr_en_m4.rs

eos_s3/intr_ctrl/
other_intr_en_m4.rs
