eos_s3/intr_ctrl/
other_intr.rs

1#[doc = "Register `OTHER_INTR` reader"]
2pub struct R(crate::R<OTHER_INTR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<OTHER_INTR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<OTHER_INTR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<OTHER_INTR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `OTHER_INTR` writer"]
17pub struct W(crate::W<OTHER_INTR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<OTHER_INTR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<OTHER_INTR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<OTHER_INTR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `M4_SRAM_INTR` reader - Interrupt detected for M4 SRAM (access during low power)"]
38pub struct M4_SRAM_INTR_R(crate::FieldReader<bool, bool>);
39impl M4_SRAM_INTR_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: bool) -> Self {
42        M4_SRAM_INTR_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for M4_SRAM_INTR_R {
46    type Target = crate::FieldReader<bool, bool>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `M4_SRAM_INTR` writer - Interrupt detected for M4 SRAM (access during low power)"]
53pub struct M4_SRAM_INTR_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> M4_SRAM_INTR_W<'a> {
57    #[doc = r"Sets the field bit"]
58    #[inline(always)]
59    pub fn set_bit(self) -> &'a mut W {
60        self.bit(true)
61    }
62    #[doc = r"Clears the field bit"]
63    #[inline(always)]
64    pub fn clear_bit(self) -> &'a mut W {
65        self.bit(false)
66    }
67    #[doc = r"Writes raw bits to the field"]
68    #[inline(always)]
69    pub fn bit(self, value: bool) -> &'a mut W {
70        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
71        self.w
72    }
73}
74#[doc = "Field `UART_INTR` reader - Interrupt detected for UART"]
75pub struct UART_INTR_R(crate::FieldReader<bool, bool>);
76impl UART_INTR_R {
77    #[inline(always)]
78    pub(crate) fn new(bits: bool) -> Self {
79        UART_INTR_R(crate::FieldReader::new(bits))
80    }
81}
82impl core::ops::Deref for UART_INTR_R {
83    type Target = crate::FieldReader<bool, bool>;
84    #[inline(always)]
85    fn deref(&self) -> &Self::Target {
86        &self.0
87    }
88}
89#[doc = "Field `UART_INTR` writer - Interrupt detected for UART"]
90pub struct UART_INTR_W<'a> {
91    w: &'a mut W,
92}
93impl<'a> UART_INTR_W<'a> {
94    #[doc = r"Sets the field bit"]
95    #[inline(always)]
96    pub fn set_bit(self) -> &'a mut W {
97        self.bit(true)
98    }
99    #[doc = r"Clears the field bit"]
100    #[inline(always)]
101    pub fn clear_bit(self) -> &'a mut W {
102        self.bit(false)
103    }
104    #[doc = r"Writes raw bits to the field"]
105    #[inline(always)]
106    pub fn bit(self, value: bool) -> &'a mut W {
107        self.w.bits =
108            (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
109        self.w
110    }
111}
112#[doc = "Field `TIMER_INTR` reader - Interrupt detected for timer"]
113pub struct TIMER_INTR_R(crate::FieldReader<bool, bool>);
114impl TIMER_INTR_R {
115    #[inline(always)]
116    pub(crate) fn new(bits: bool) -> Self {
117        TIMER_INTR_R(crate::FieldReader::new(bits))
118    }
119}
120impl core::ops::Deref for TIMER_INTR_R {
121    type Target = crate::FieldReader<bool, bool>;
122    #[inline(always)]
123    fn deref(&self) -> &Self::Target {
124        &self.0
125    }
126}
127#[doc = "Field `TIMER_INTR` writer - Interrupt detected for timer"]
128pub struct TIMER_INTR_W<'a> {
129    w: &'a mut W,
130}
131impl<'a> TIMER_INTR_W<'a> {
132    #[doc = r"Sets the field bit"]
133    #[inline(always)]
134    pub fn set_bit(self) -> &'a mut W {
135        self.bit(true)
136    }
137    #[doc = r"Clears the field bit"]
138    #[inline(always)]
139    pub fn clear_bit(self) -> &'a mut W {
140        self.bit(false)
141    }
142    #[doc = r"Writes raw bits to the field"]
143    #[inline(always)]
144    pub fn bit(self, value: bool) -> &'a mut W {
145        self.w.bits =
146            (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
147        self.w
148    }
149}
150#[doc = "Field `WDOG_INTR` reader - Interrupt detected for WDT M4"]
151pub struct WDOG_INTR_R(crate::FieldReader<bool, bool>);
152impl WDOG_INTR_R {
153    #[inline(always)]
154    pub(crate) fn new(bits: bool) -> Self {
155        WDOG_INTR_R(crate::FieldReader::new(bits))
156    }
157}
158impl core::ops::Deref for WDOG_INTR_R {
159    type Target = crate::FieldReader<bool, bool>;
160    #[inline(always)]
161    fn deref(&self) -> &Self::Target {
162        &self.0
163    }
164}
165#[doc = "Field `WDOG_INTR` writer - Interrupt detected for WDT M4"]
166pub struct WDOG_INTR_W<'a> {
167    w: &'a mut W,
168}
169impl<'a> WDOG_INTR_W<'a> {
170    #[doc = r"Sets the field bit"]
171    #[inline(always)]
172    pub fn set_bit(self) -> &'a mut W {
173        self.bit(true)
174    }
175    #[doc = r"Clears the field bit"]
176    #[inline(always)]
177    pub fn clear_bit(self) -> &'a mut W {
178        self.bit(false)
179    }
180    #[doc = r"Writes raw bits to the field"]
181    #[inline(always)]
182    pub fn bit(self, value: bool) -> &'a mut W {
183        self.w.bits =
184            (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
185        self.w
186    }
187}
188#[doc = "Field `WDOG_RST` reader - Interrupt detected for WDT M4 Reset"]
189pub struct WDOG_RST_R(crate::FieldReader<bool, bool>);
190impl WDOG_RST_R {
191    #[inline(always)]
192    pub(crate) fn new(bits: bool) -> Self {
193        WDOG_RST_R(crate::FieldReader::new(bits))
194    }
195}
196impl core::ops::Deref for WDOG_RST_R {
197    type Target = crate::FieldReader<bool, bool>;
198    #[inline(always)]
199    fn deref(&self) -> &Self::Target {
200        &self.0
201    }
202}
203#[doc = "Field `WDOG_RST` writer - Interrupt detected for WDT M4 Reset"]
204pub struct WDOG_RST_W<'a> {
205    w: &'a mut W,
206}
207impl<'a> WDOG_RST_W<'a> {
208    #[doc = r"Sets the field bit"]
209    #[inline(always)]
210    pub fn set_bit(self) -> &'a mut W {
211        self.bit(true)
212    }
213    #[doc = r"Clears the field bit"]
214    #[inline(always)]
215    pub fn clear_bit(self) -> &'a mut W {
216        self.bit(false)
217    }
218    #[doc = r"Writes raw bits to the field"]
219    #[inline(always)]
220    pub fn bit(self, value: bool) -> &'a mut W {
221        self.w.bits =
222            (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
223        self.w
224    }
225}
226#[doc = "Field `TIMEOUT_INTR` reader - Interrupt detected for bus timeout"]
227pub struct TIMEOUT_INTR_R(crate::FieldReader<bool, bool>);
228impl TIMEOUT_INTR_R {
229    #[inline(always)]
230    pub(crate) fn new(bits: bool) -> Self {
231        TIMEOUT_INTR_R(crate::FieldReader::new(bits))
232    }
233}
234impl core::ops::Deref for TIMEOUT_INTR_R {
235    type Target = crate::FieldReader<bool, bool>;
236    #[inline(always)]
237    fn deref(&self) -> &Self::Target {
238        &self.0
239    }
240}
241#[doc = "Field `TIMEOUT_INTR` writer - Interrupt detected for bus timeout"]
242pub struct TIMEOUT_INTR_W<'a> {
243    w: &'a mut W,
244}
245impl<'a> TIMEOUT_INTR_W<'a> {
246    #[doc = r"Sets the field bit"]
247    #[inline(always)]
248    pub fn set_bit(self) -> &'a mut W {
249        self.bit(true)
250    }
251    #[doc = r"Clears the field bit"]
252    #[inline(always)]
253    pub fn clear_bit(self) -> &'a mut W {
254        self.bit(false)
255    }
256    #[doc = r"Writes raw bits to the field"]
257    #[inline(always)]
258    pub fn bit(self, value: bool) -> &'a mut W {
259        self.w.bits =
260            (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
261        self.w
262    }
263}
264#[doc = "Field `FPU_INTR` reader - Interrupt detected for M4 FPU"]
265pub struct FPU_INTR_R(crate::FieldReader<bool, bool>);
266impl FPU_INTR_R {
267    #[inline(always)]
268    pub(crate) fn new(bits: bool) -> Self {
269        FPU_INTR_R(crate::FieldReader::new(bits))
270    }
271}
272impl core::ops::Deref for FPU_INTR_R {
273    type Target = crate::FieldReader<bool, bool>;
274    #[inline(always)]
275    fn deref(&self) -> &Self::Target {
276        &self.0
277    }
278}
279#[doc = "Field `FPU_INTR` writer - Interrupt detected for M4 FPU"]
280pub struct FPU_INTR_W<'a> {
281    w: &'a mut W,
282}
283impl<'a> FPU_INTR_W<'a> {
284    #[doc = r"Sets the field bit"]
285    #[inline(always)]
286    pub fn set_bit(self) -> &'a mut W {
287        self.bit(true)
288    }
289    #[doc = r"Clears the field bit"]
290    #[inline(always)]
291    pub fn clear_bit(self) -> &'a mut W {
292        self.bit(false)
293    }
294    #[doc = r"Writes raw bits to the field"]
295    #[inline(always)]
296    pub fn bit(self, value: bool) -> &'a mut W {
297        self.w.bits =
298            (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
299        self.w
300    }
301}
302#[doc = "Field `PKFB_INTR` reader - Interrupt detected for Packet FIFO Bank"]
303pub struct PKFB_INTR_R(crate::FieldReader<bool, bool>);
304impl PKFB_INTR_R {
305    #[inline(always)]
306    pub(crate) fn new(bits: bool) -> Self {
307        PKFB_INTR_R(crate::FieldReader::new(bits))
308    }
309}
310impl core::ops::Deref for PKFB_INTR_R {
311    type Target = crate::FieldReader<bool, bool>;
312    #[inline(always)]
313    fn deref(&self) -> &Self::Target {
314        &self.0
315    }
316}
317#[doc = "Field `PKFB_INTR` writer - Interrupt detected for Packet FIFO Bank"]
318pub struct PKFB_INTR_W<'a> {
319    w: &'a mut W,
320}
321impl<'a> PKFB_INTR_W<'a> {
322    #[doc = r"Sets the field bit"]
323    #[inline(always)]
324    pub fn set_bit(self) -> &'a mut W {
325        self.bit(true)
326    }
327    #[doc = r"Clears the field bit"]
328    #[inline(always)]
329    pub fn clear_bit(self) -> &'a mut W {
330        self.bit(false)
331    }
332    #[doc = r"Writes raw bits to the field"]
333    #[inline(always)]
334    pub fn bit(self, value: bool) -> &'a mut W {
335        self.w.bits =
336            (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
337        self.w
338    }
339}
340#[doc = "Field `SPI_MS_INTR` reader - Interrupt detected for SPI Master"]
341pub struct SPI_MS_INTR_R(crate::FieldReader<bool, bool>);
342impl SPI_MS_INTR_R {
343    #[inline(always)]
344    pub(crate) fn new(bits: bool) -> Self {
345        SPI_MS_INTR_R(crate::FieldReader::new(bits))
346    }
347}
348impl core::ops::Deref for SPI_MS_INTR_R {
349    type Target = crate::FieldReader<bool, bool>;
350    #[inline(always)]
351    fn deref(&self) -> &Self::Target {
352        &self.0
353    }
354}
355#[doc = "Field `SPI_MS_INTR` writer - Interrupt detected for SPI Master"]
356pub struct SPI_MS_INTR_W<'a> {
357    w: &'a mut W,
358}
359impl<'a> SPI_MS_INTR_W<'a> {
360    #[doc = r"Sets the field bit"]
361    #[inline(always)]
362    pub fn set_bit(self) -> &'a mut W {
363        self.bit(true)
364    }
365    #[doc = r"Clears the field bit"]
366    #[inline(always)]
367    pub fn clear_bit(self) -> &'a mut W {
368        self.bit(false)
369    }
370    #[doc = r"Writes raw bits to the field"]
371    #[inline(always)]
372    pub fn bit(self, value: bool) -> &'a mut W {
373        self.w.bits =
374            (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
375        self.w
376    }
377}
378#[doc = "Field `CFG_DMA_INTR` reader - Interrupt detected for Config DMA"]
379pub struct CFG_DMA_INTR_R(crate::FieldReader<bool, bool>);
380impl CFG_DMA_INTR_R {
381    #[inline(always)]
382    pub(crate) fn new(bits: bool) -> Self {
383        CFG_DMA_INTR_R(crate::FieldReader::new(bits))
384    }
385}
386impl core::ops::Deref for CFG_DMA_INTR_R {
387    type Target = crate::FieldReader<bool, bool>;
388    #[inline(always)]
389    fn deref(&self) -> &Self::Target {
390        &self.0
391    }
392}
393#[doc = "Field `CFG_DMA_INTR` writer - Interrupt detected for Config DMA"]
394pub struct CFG_DMA_INTR_W<'a> {
395    w: &'a mut W,
396}
397impl<'a> CFG_DMA_INTR_W<'a> {
398    #[doc = r"Sets the field bit"]
399    #[inline(always)]
400    pub fn set_bit(self) -> &'a mut W {
401        self.bit(true)
402    }
403    #[doc = r"Clears the field bit"]
404    #[inline(always)]
405    pub fn clear_bit(self) -> &'a mut W {
406        self.bit(false)
407    }
408    #[doc = r"Writes raw bits to the field"]
409    #[inline(always)]
410    pub fn bit(self, value: bool) -> &'a mut W {
411        self.w.bits =
412            (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
413        self.w
414    }
415}
416#[doc = "Field `PMU_TMR_INTR` reader - Interrupt detected for PMU Timer"]
417pub struct PMU_TMR_INTR_R(crate::FieldReader<bool, bool>);
418impl PMU_TMR_INTR_R {
419    #[inline(always)]
420    pub(crate) fn new(bits: bool) -> Self {
421        PMU_TMR_INTR_R(crate::FieldReader::new(bits))
422    }
423}
424impl core::ops::Deref for PMU_TMR_INTR_R {
425    type Target = crate::FieldReader<bool, bool>;
426    #[inline(always)]
427    fn deref(&self) -> &Self::Target {
428        &self.0
429    }
430}
431#[doc = "Field `PMU_TMR_INTR` writer - Interrupt detected for PMU Timer"]
432pub struct PMU_TMR_INTR_W<'a> {
433    w: &'a mut W,
434}
435impl<'a> PMU_TMR_INTR_W<'a> {
436    #[doc = r"Sets the field bit"]
437    #[inline(always)]
438    pub fn set_bit(self) -> &'a mut W {
439        self.bit(true)
440    }
441    #[doc = r"Clears the field bit"]
442    #[inline(always)]
443    pub fn clear_bit(self) -> &'a mut W {
444        self.bit(false)
445    }
446    #[doc = r"Writes raw bits to the field"]
447    #[inline(always)]
448    pub fn bit(self, value: bool) -> &'a mut W {
449        self.w.bits =
450            (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
451        self.w
452    }
453}
454#[doc = "Field `ADC_INTR` reader - Interrupt detected for ADC"]
455pub struct ADC_INTR_R(crate::FieldReader<bool, bool>);
456impl ADC_INTR_R {
457    #[inline(always)]
458    pub(crate) fn new(bits: bool) -> Self {
459        ADC_INTR_R(crate::FieldReader::new(bits))
460    }
461}
462impl core::ops::Deref for ADC_INTR_R {
463    type Target = crate::FieldReader<bool, bool>;
464    #[inline(always)]
465    fn deref(&self) -> &Self::Target {
466        &self.0
467    }
468}
469#[doc = "Field `ADC_INTR` writer - Interrupt detected for ADC"]
470pub struct ADC_INTR_W<'a> {
471    w: &'a mut W,
472}
473impl<'a> ADC_INTR_W<'a> {
474    #[doc = r"Sets the field bit"]
475    #[inline(always)]
476    pub fn set_bit(self) -> &'a mut W {
477        self.bit(true)
478    }
479    #[doc = r"Clears the field bit"]
480    #[inline(always)]
481    pub fn clear_bit(self) -> &'a mut W {
482        self.bit(false)
483    }
484    #[doc = r"Writes raw bits to the field"]
485    #[inline(always)]
486    pub fn bit(self, value: bool) -> &'a mut W {
487        self.w.bits =
488            (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
489        self.w
490    }
491}
492#[doc = "Field `RTC_INTR` reader - Interrupt detected for RTC"]
493pub struct RTC_INTR_R(crate::FieldReader<bool, bool>);
494impl RTC_INTR_R {
495    #[inline(always)]
496    pub(crate) fn new(bits: bool) -> Self {
497        RTC_INTR_R(crate::FieldReader::new(bits))
498    }
499}
500impl core::ops::Deref for RTC_INTR_R {
501    type Target = crate::FieldReader<bool, bool>;
502    #[inline(always)]
503    fn deref(&self) -> &Self::Target {
504        &self.0
505    }
506}
507#[doc = "Field `RTC_INTR` writer - Interrupt detected for RTC"]
508pub struct RTC_INTR_W<'a> {
509    w: &'a mut W,
510}
511impl<'a> RTC_INTR_W<'a> {
512    #[doc = r"Sets the field bit"]
513    #[inline(always)]
514    pub fn set_bit(self) -> &'a mut W {
515        self.bit(true)
516    }
517    #[doc = r"Clears the field bit"]
518    #[inline(always)]
519    pub fn clear_bit(self) -> &'a mut W {
520        self.bit(false)
521    }
522    #[doc = r"Writes raw bits to the field"]
523    #[inline(always)]
524    pub fn bit(self, value: bool) -> &'a mut W {
525        self.w.bits =
526            (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
527        self.w
528    }
529}
530#[doc = "Field `RST_INTR` reader - Interrupt detected for Reset"]
531pub struct RST_INTR_R(crate::FieldReader<bool, bool>);
532impl RST_INTR_R {
533    #[inline(always)]
534    pub(crate) fn new(bits: bool) -> Self {
535        RST_INTR_R(crate::FieldReader::new(bits))
536    }
537}
538impl core::ops::Deref for RST_INTR_R {
539    type Target = crate::FieldReader<bool, bool>;
540    #[inline(always)]
541    fn deref(&self) -> &Self::Target {
542        &self.0
543    }
544}
545#[doc = "Field `RST_INTR` writer - Interrupt detected for Reset"]
546pub struct RST_INTR_W<'a> {
547    w: &'a mut W,
548}
549impl<'a> RST_INTR_W<'a> {
550    #[doc = r"Sets the field bit"]
551    #[inline(always)]
552    pub fn set_bit(self) -> &'a mut W {
553        self.bit(true)
554    }
555    #[doc = r"Clears the field bit"]
556    #[inline(always)]
557    pub fn clear_bit(self) -> &'a mut W {
558        self.bit(false)
559    }
560    #[doc = r"Writes raw bits to the field"]
561    #[inline(always)]
562    pub fn bit(self, value: bool) -> &'a mut W {
563        self.w.bits =
564            (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
565        self.w
566    }
567}
568#[doc = "Field `FFE0_INTR_OTHERS` reader - Interrupt detected for FFE0 other interrupts"]
569pub struct FFE0_INTR_OTHERS_R(crate::FieldReader<bool, bool>);
570impl FFE0_INTR_OTHERS_R {
571    #[inline(always)]
572    pub(crate) fn new(bits: bool) -> Self {
573        FFE0_INTR_OTHERS_R(crate::FieldReader::new(bits))
574    }
575}
576impl core::ops::Deref for FFE0_INTR_OTHERS_R {
577    type Target = crate::FieldReader<bool, bool>;
578    #[inline(always)]
579    fn deref(&self) -> &Self::Target {
580        &self.0
581    }
582}
583#[doc = "Field `FFE0_INTR_OTHERS` writer - Interrupt detected for FFE0 other interrupts"]
584pub struct FFE0_INTR_OTHERS_W<'a> {
585    w: &'a mut W,
586}
587impl<'a> FFE0_INTR_OTHERS_W<'a> {
588    #[doc = r"Sets the field bit"]
589    #[inline(always)]
590    pub fn set_bit(self) -> &'a mut W {
591        self.bit(true)
592    }
593    #[doc = r"Clears the field bit"]
594    #[inline(always)]
595    pub fn clear_bit(self) -> &'a mut W {
596        self.bit(false)
597    }
598    #[doc = r"Writes raw bits to the field"]
599    #[inline(always)]
600    pub fn bit(self, value: bool) -> &'a mut W {
601        self.w.bits =
602            (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
603        self.w
604    }
605}
606#[doc = "Field `APBOOT_EN_INTR` reader - Interrupt detected for AP boot"]
607pub struct APBOOT_EN_INTR_R(crate::FieldReader<bool, bool>);
608impl APBOOT_EN_INTR_R {
609    #[inline(always)]
610    pub(crate) fn new(bits: bool) -> Self {
611        APBOOT_EN_INTR_R(crate::FieldReader::new(bits))
612    }
613}
614impl core::ops::Deref for APBOOT_EN_INTR_R {
615    type Target = crate::FieldReader<bool, bool>;
616    #[inline(always)]
617    fn deref(&self) -> &Self::Target {
618        &self.0
619    }
620}
621#[doc = "Field `APBOOT_EN_INTR` writer - Interrupt detected for AP boot"]
622pub struct APBOOT_EN_INTR_W<'a> {
623    w: &'a mut W,
624}
625impl<'a> APBOOT_EN_INTR_W<'a> {
626    #[doc = r"Sets the field bit"]
627    #[inline(always)]
628    pub fn set_bit(self) -> &'a mut W {
629        self.bit(true)
630    }
631    #[doc = r"Clears the field bit"]
632    #[inline(always)]
633    pub fn clear_bit(self) -> &'a mut W {
634        self.bit(false)
635    }
636    #[doc = r"Writes raw bits to the field"]
637    #[inline(always)]
638    pub fn bit(self, value: bool) -> &'a mut W {
639        self.w.bits =
640            (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
641        self.w
642    }
643}
644#[doc = "Field `LDO30_PG_INTR` reader - Interrupt detected for absence of LDO30 power good"]
645pub struct LDO30_PG_INTR_R(crate::FieldReader<bool, bool>);
646impl LDO30_PG_INTR_R {
647    #[inline(always)]
648    pub(crate) fn new(bits: bool) -> Self {
649        LDO30_PG_INTR_R(crate::FieldReader::new(bits))
650    }
651}
652impl core::ops::Deref for LDO30_PG_INTR_R {
653    type Target = crate::FieldReader<bool, bool>;
654    #[inline(always)]
655    fn deref(&self) -> &Self::Target {
656        &self.0
657    }
658}
659#[doc = "Field `LDO30_PG_INTR` writer - Interrupt detected for absence of LDO30 power good"]
660pub struct LDO30_PG_INTR_W<'a> {
661    w: &'a mut W,
662}
663impl<'a> LDO30_PG_INTR_W<'a> {
664    #[doc = r"Sets the field bit"]
665    #[inline(always)]
666    pub fn set_bit(self) -> &'a mut W {
667        self.bit(true)
668    }
669    #[doc = r"Clears the field bit"]
670    #[inline(always)]
671    pub fn clear_bit(self) -> &'a mut W {
672        self.bit(false)
673    }
674    #[doc = r"Writes raw bits to the field"]
675    #[inline(always)]
676    pub fn bit(self, value: bool) -> &'a mut W {
677        self.w.bits =
678            (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
679        self.w
680    }
681}
682#[doc = "Field `LDO50_PG_INTR` reader - Interrupt detected for absence of LDO30 power good"]
683pub struct LDO50_PG_INTR_R(crate::FieldReader<bool, bool>);
684impl LDO50_PG_INTR_R {
685    #[inline(always)]
686    pub(crate) fn new(bits: bool) -> Self {
687        LDO50_PG_INTR_R(crate::FieldReader::new(bits))
688    }
689}
690impl core::ops::Deref for LDO50_PG_INTR_R {
691    type Target = crate::FieldReader<bool, bool>;
692    #[inline(always)]
693    fn deref(&self) -> &Self::Target {
694        &self.0
695    }
696}
697#[doc = "Field `LDO50_PG_INTR` writer - Interrupt detected for absence of LDO30 power good"]
698pub struct LDO50_PG_INTR_W<'a> {
699    w: &'a mut W,
700}
701impl<'a> LDO50_PG_INTR_W<'a> {
702    #[doc = r"Sets the field bit"]
703    #[inline(always)]
704    pub fn set_bit(self) -> &'a mut W {
705        self.bit(true)
706    }
707    #[doc = r"Clears the field bit"]
708    #[inline(always)]
709    pub fn clear_bit(self) -> &'a mut W {
710        self.bit(false)
711    }
712    #[doc = r"Writes raw bits to the field"]
713    #[inline(always)]
714    pub fn bit(self, value: bool) -> &'a mut W {
715        self.w.bits =
716            (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
717        self.w
718    }
719}
720#[doc = "Field `LPSD_VOICE_DET` reader - Interrupt detected for LPSD Voice"]
721pub struct LPSD_VOICE_DET_R(crate::FieldReader<bool, bool>);
722impl LPSD_VOICE_DET_R {
723    #[inline(always)]
724    pub(crate) fn new(bits: bool) -> Self {
725        LPSD_VOICE_DET_R(crate::FieldReader::new(bits))
726    }
727}
728impl core::ops::Deref for LPSD_VOICE_DET_R {
729    type Target = crate::FieldReader<bool, bool>;
730    #[inline(always)]
731    fn deref(&self) -> &Self::Target {
732        &self.0
733    }
734}
735#[doc = "Field `LPSD_VOICE_DET` writer - Interrupt detected for LPSD Voice"]
736pub struct LPSD_VOICE_DET_W<'a> {
737    w: &'a mut W,
738}
739impl<'a> LPSD_VOICE_DET_W<'a> {
740    #[doc = r"Sets the field bit"]
741    #[inline(always)]
742    pub fn set_bit(self) -> &'a mut W {
743        self.bit(true)
744    }
745    #[doc = r"Clears the field bit"]
746    #[inline(always)]
747    pub fn clear_bit(self) -> &'a mut W {
748        self.bit(false)
749    }
750    #[doc = r"Writes raw bits to the field"]
751    #[inline(always)]
752    pub fn bit(self, value: bool) -> &'a mut W {
753        self.w.bits =
754            (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
755        self.w
756    }
757}
758#[doc = "Field `DMIC_VOICE_DET` reader - Interrupt detected for Digital MIC"]
759pub struct DMIC_VOICE_DET_R(crate::FieldReader<bool, bool>);
760impl DMIC_VOICE_DET_R {
761    #[inline(always)]
762    pub(crate) fn new(bits: bool) -> Self {
763        DMIC_VOICE_DET_R(crate::FieldReader::new(bits))
764    }
765}
766impl core::ops::Deref for DMIC_VOICE_DET_R {
767    type Target = crate::FieldReader<bool, bool>;
768    #[inline(always)]
769    fn deref(&self) -> &Self::Target {
770        &self.0
771    }
772}
773#[doc = "Field `DMIC_VOICE_DET` writer - Interrupt detected for Digital MIC"]
774pub struct DMIC_VOICE_DET_W<'a> {
775    w: &'a mut W,
776}
777impl<'a> DMIC_VOICE_DET_W<'a> {
778    #[doc = r"Sets the field bit"]
779    #[inline(always)]
780    pub fn set_bit(self) -> &'a mut W {
781        self.bit(true)
782    }
783    #[doc = r"Clears the field bit"]
784    #[inline(always)]
785    pub fn clear_bit(self) -> &'a mut W {
786        self.bit(false)
787    }
788    #[doc = r"Writes raw bits to the field"]
789    #[inline(always)]
790    pub fn bit(self, value: bool) -> &'a mut W {
791        self.w.bits =
792            (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
793        self.w
794    }
795}
796impl R {
797    #[doc = "Bit 0 - Interrupt detected for M4 SRAM (access during low power)"]
798    #[inline(always)]
799    pub fn m4_sram_intr(&self) -> M4_SRAM_INTR_R {
800        M4_SRAM_INTR_R::new((self.bits & 0x01) != 0)
801    }
802    #[doc = "Bit 1 - Interrupt detected for UART"]
803    #[inline(always)]
804    pub fn uart_intr(&self) -> UART_INTR_R {
805        UART_INTR_R::new(((self.bits >> 1) & 0x01) != 0)
806    }
807    #[doc = "Bit 2 - Interrupt detected for timer"]
808    #[inline(always)]
809    pub fn timer_intr(&self) -> TIMER_INTR_R {
810        TIMER_INTR_R::new(((self.bits >> 2) & 0x01) != 0)
811    }
812    #[doc = "Bit 3 - Interrupt detected for WDT M4"]
813    #[inline(always)]
814    pub fn wdog_intr(&self) -> WDOG_INTR_R {
815        WDOG_INTR_R::new(((self.bits >> 3) & 0x01) != 0)
816    }
817    #[doc = "Bit 4 - Interrupt detected for WDT M4 Reset"]
818    #[inline(always)]
819    pub fn wdog_rst(&self) -> WDOG_RST_R {
820        WDOG_RST_R::new(((self.bits >> 4) & 0x01) != 0)
821    }
822    #[doc = "Bit 5 - Interrupt detected for bus timeout"]
823    #[inline(always)]
824    pub fn timeout_intr(&self) -> TIMEOUT_INTR_R {
825        TIMEOUT_INTR_R::new(((self.bits >> 5) & 0x01) != 0)
826    }
827    #[doc = "Bit 6 - Interrupt detected for M4 FPU"]
828    #[inline(always)]
829    pub fn fpu_intr(&self) -> FPU_INTR_R {
830        FPU_INTR_R::new(((self.bits >> 6) & 0x01) != 0)
831    }
832    #[doc = "Bit 7 - Interrupt detected for Packet FIFO Bank"]
833    #[inline(always)]
834    pub fn pkfb_intr(&self) -> PKFB_INTR_R {
835        PKFB_INTR_R::new(((self.bits >> 7) & 0x01) != 0)
836    }
837    #[doc = "Bit 10 - Interrupt detected for SPI Master"]
838    #[inline(always)]
839    pub fn spi_ms_intr(&self) -> SPI_MS_INTR_R {
840        SPI_MS_INTR_R::new(((self.bits >> 10) & 0x01) != 0)
841    }
842    #[doc = "Bit 11 - Interrupt detected for Config DMA"]
843    #[inline(always)]
844    pub fn cfg_dma_intr(&self) -> CFG_DMA_INTR_R {
845        CFG_DMA_INTR_R::new(((self.bits >> 11) & 0x01) != 0)
846    }
847    #[doc = "Bit 12 - Interrupt detected for PMU Timer"]
848    #[inline(always)]
849    pub fn pmu_tmr_intr(&self) -> PMU_TMR_INTR_R {
850        PMU_TMR_INTR_R::new(((self.bits >> 12) & 0x01) != 0)
851    }
852    #[doc = "Bit 13 - Interrupt detected for ADC"]
853    #[inline(always)]
854    pub fn adc_intr(&self) -> ADC_INTR_R {
855        ADC_INTR_R::new(((self.bits >> 13) & 0x01) != 0)
856    }
857    #[doc = "Bit 14 - Interrupt detected for RTC"]
858    #[inline(always)]
859    pub fn rtc_intr(&self) -> RTC_INTR_R {
860        RTC_INTR_R::new(((self.bits >> 14) & 0x01) != 0)
861    }
862    #[doc = "Bit 15 - Interrupt detected for Reset"]
863    #[inline(always)]
864    pub fn rst_intr(&self) -> RST_INTR_R {
865        RST_INTR_R::new(((self.bits >> 15) & 0x01) != 0)
866    }
867    #[doc = "Bit 16 - Interrupt detected for FFE0 other interrupts"]
868    #[inline(always)]
869    pub fn ffe0_intr_others(&self) -> FFE0_INTR_OTHERS_R {
870        FFE0_INTR_OTHERS_R::new(((self.bits >> 16) & 0x01) != 0)
871    }
872    #[doc = "Bit 18 - Interrupt detected for AP boot"]
873    #[inline(always)]
874    pub fn apboot_en_intr(&self) -> APBOOT_EN_INTR_R {
875        APBOOT_EN_INTR_R::new(((self.bits >> 18) & 0x01) != 0)
876    }
877    #[doc = "Bit 19 - Interrupt detected for absence of LDO30 power good"]
878    #[inline(always)]
879    pub fn ldo30_pg_intr(&self) -> LDO30_PG_INTR_R {
880        LDO30_PG_INTR_R::new(((self.bits >> 19) & 0x01) != 0)
881    }
882    #[doc = "Bit 20 - Interrupt detected for absence of LDO30 power good"]
883    #[inline(always)]
884    pub fn ldo50_pg_intr(&self) -> LDO50_PG_INTR_R {
885        LDO50_PG_INTR_R::new(((self.bits >> 20) & 0x01) != 0)
886    }
887    #[doc = "Bit 22 - Interrupt detected for LPSD Voice"]
888    #[inline(always)]
889    pub fn lpsd_voice_det(&self) -> LPSD_VOICE_DET_R {
890        LPSD_VOICE_DET_R::new(((self.bits >> 22) & 0x01) != 0)
891    }
892    #[doc = "Bit 23 - Interrupt detected for Digital MIC"]
893    #[inline(always)]
894    pub fn dmic_voice_det(&self) -> DMIC_VOICE_DET_R {
895        DMIC_VOICE_DET_R::new(((self.bits >> 23) & 0x01) != 0)
896    }
897}
898impl W {
899    #[doc = "Bit 0 - Interrupt detected for M4 SRAM (access during low power)"]
900    #[inline(always)]
901    pub fn m4_sram_intr(&mut self) -> M4_SRAM_INTR_W {
902        M4_SRAM_INTR_W { w: self }
903    }
904    #[doc = "Bit 1 - Interrupt detected for UART"]
905    #[inline(always)]
906    pub fn uart_intr(&mut self) -> UART_INTR_W {
907        UART_INTR_W { w: self }
908    }
909    #[doc = "Bit 2 - Interrupt detected for timer"]
910    #[inline(always)]
911    pub fn timer_intr(&mut self) -> TIMER_INTR_W {
912        TIMER_INTR_W { w: self }
913    }
914    #[doc = "Bit 3 - Interrupt detected for WDT M4"]
915    #[inline(always)]
916    pub fn wdog_intr(&mut self) -> WDOG_INTR_W {
917        WDOG_INTR_W { w: self }
918    }
919    #[doc = "Bit 4 - Interrupt detected for WDT M4 Reset"]
920    #[inline(always)]
921    pub fn wdog_rst(&mut self) -> WDOG_RST_W {
922        WDOG_RST_W { w: self }
923    }
924    #[doc = "Bit 5 - Interrupt detected for bus timeout"]
925    #[inline(always)]
926    pub fn timeout_intr(&mut self) -> TIMEOUT_INTR_W {
927        TIMEOUT_INTR_W { w: self }
928    }
929    #[doc = "Bit 6 - Interrupt detected for M4 FPU"]
930    #[inline(always)]
931    pub fn fpu_intr(&mut self) -> FPU_INTR_W {
932        FPU_INTR_W { w: self }
933    }
934    #[doc = "Bit 7 - Interrupt detected for Packet FIFO Bank"]
935    #[inline(always)]
936    pub fn pkfb_intr(&mut self) -> PKFB_INTR_W {
937        PKFB_INTR_W { w: self }
938    }
939    #[doc = "Bit 10 - Interrupt detected for SPI Master"]
940    #[inline(always)]
941    pub fn spi_ms_intr(&mut self) -> SPI_MS_INTR_W {
942        SPI_MS_INTR_W { w: self }
943    }
944    #[doc = "Bit 11 - Interrupt detected for Config DMA"]
945    #[inline(always)]
946    pub fn cfg_dma_intr(&mut self) -> CFG_DMA_INTR_W {
947        CFG_DMA_INTR_W { w: self }
948    }
949    #[doc = "Bit 12 - Interrupt detected for PMU Timer"]
950    #[inline(always)]
951    pub fn pmu_tmr_intr(&mut self) -> PMU_TMR_INTR_W {
952        PMU_TMR_INTR_W { w: self }
953    }
954    #[doc = "Bit 13 - Interrupt detected for ADC"]
955    #[inline(always)]
956    pub fn adc_intr(&mut self) -> ADC_INTR_W {
957        ADC_INTR_W { w: self }
958    }
959    #[doc = "Bit 14 - Interrupt detected for RTC"]
960    #[inline(always)]
961    pub fn rtc_intr(&mut self) -> RTC_INTR_W {
962        RTC_INTR_W { w: self }
963    }
964    #[doc = "Bit 15 - Interrupt detected for Reset"]
965    #[inline(always)]
966    pub fn rst_intr(&mut self) -> RST_INTR_W {
967        RST_INTR_W { w: self }
968    }
969    #[doc = "Bit 16 - Interrupt detected for FFE0 other interrupts"]
970    #[inline(always)]
971    pub fn ffe0_intr_others(&mut self) -> FFE0_INTR_OTHERS_W {
972        FFE0_INTR_OTHERS_W { w: self }
973    }
974    #[doc = "Bit 18 - Interrupt detected for AP boot"]
975    #[inline(always)]
976    pub fn apboot_en_intr(&mut self) -> APBOOT_EN_INTR_W {
977        APBOOT_EN_INTR_W { w: self }
978    }
979    #[doc = "Bit 19 - Interrupt detected for absence of LDO30 power good"]
980    #[inline(always)]
981    pub fn ldo30_pg_intr(&mut self) -> LDO30_PG_INTR_W {
982        LDO30_PG_INTR_W { w: self }
983    }
984    #[doc = "Bit 20 - Interrupt detected for absence of LDO30 power good"]
985    #[inline(always)]
986    pub fn ldo50_pg_intr(&mut self) -> LDO50_PG_INTR_W {
987        LDO50_PG_INTR_W { w: self }
988    }
989    #[doc = "Bit 22 - Interrupt detected for LPSD Voice"]
990    #[inline(always)]
991    pub fn lpsd_voice_det(&mut self) -> LPSD_VOICE_DET_W {
992        LPSD_VOICE_DET_W { w: self }
993    }
994    #[doc = "Bit 23 - Interrupt detected for Digital MIC"]
995    #[inline(always)]
996    pub fn dmic_voice_det(&mut self) -> DMIC_VOICE_DET_W {
997        DMIC_VOICE_DET_W { w: self }
998    }
999    #[doc = "Writes raw bits to the register."]
1000    #[inline(always)]
1001    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1002        self.0.bits(bits);
1003        self
1004    }
1005}
1006#[doc = "Indicators of interrupt triggers detected\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [other_intr](index.html) module"]
1007pub struct OTHER_INTR_SPEC;
1008impl crate::RegisterSpec for OTHER_INTR_SPEC {
1009    type Ux = u32;
1010}
1011#[doc = "`read()` method returns [other_intr::R](R) reader structure"]
1012impl crate::Readable for OTHER_INTR_SPEC {
1013    type Reader = R;
1014}
1015#[doc = "`write(|w| ..)` method takes [other_intr::W](W) writer structure"]
1016impl crate::Writable for OTHER_INTR_SPEC {
1017    type Writer = W;
1018}
1019#[doc = "`reset()` method sets OTHER_INTR to value 0"]
1020impl crate::Resettable for OTHER_INTR_SPEC {
1021    #[inline(always)]
1022    fn reset_value() -> Self::Ux {
1023        0
1024    }
1025}
eos_s3/intr_ctrl/other_intr.rs

eos_s3/intr_ctrl/
other_intr.rs
