eos_s3/extm4regs/
m4_mem_int.rs

1#[doc = "Register `M4_MEM_INT` reader"]
2pub struct R(crate::R<M4_MEM_INT_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<M4_MEM_INT_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<M4_MEM_INT_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<M4_MEM_INT_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `M4_MEM_INT` writer"]
17pub struct W(crate::W<M4_MEM_INT_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<M4_MEM_INT_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<M4_MEM_INT_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<M4_MEM_INT_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `MEMO_INTR0` reader - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_0) while it in deep sleep or shut down mode"]
38pub struct MEMO_INTR0_R(crate::FieldReader<bool, bool>);
39impl MEMO_INTR0_R {
40    #[inline(always)]
41    pub(crate) fn new(bits: bool) -> Self {
42        MEMO_INTR0_R(crate::FieldReader::new(bits))
43    }
44}
45impl core::ops::Deref for MEMO_INTR0_R {
46    type Target = crate::FieldReader<bool, bool>;
47    #[inline(always)]
48    fn deref(&self) -> &Self::Target {
49        &self.0
50    }
51}
52#[doc = "Field `MEMO_INTR0` writer - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_0) while it in deep sleep or shut down mode"]
53pub struct MEMO_INTR0_W<'a> {
54    w: &'a mut W,
55}
56impl<'a> MEMO_INTR0_W<'a> {
57    #[doc = r"Sets the field bit"]
58    #[inline(always)]
59    pub fn set_bit(self) -> &'a mut W {
60        self.bit(true)
61    }
62    #[doc = r"Clears the field bit"]
63    #[inline(always)]
64    pub fn clear_bit(self) -> &'a mut W {
65        self.bit(false)
66    }
67    #[doc = r"Writes raw bits to the field"]
68    #[inline(always)]
69    pub fn bit(self, value: bool) -> &'a mut W {
70        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
71        self.w
72    }
73}
74#[doc = "Field `MEMO_INTR1` reader - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_1) while it in deep sleep or shut down mode"]
75pub struct MEMO_INTR1_R(crate::FieldReader<bool, bool>);
76impl MEMO_INTR1_R {
77    #[inline(always)]
78    pub(crate) fn new(bits: bool) -> Self {
79        MEMO_INTR1_R(crate::FieldReader::new(bits))
80    }
81}
82impl core::ops::Deref for MEMO_INTR1_R {
83    type Target = crate::FieldReader<bool, bool>;
84    #[inline(always)]
85    fn deref(&self) -> &Self::Target {
86        &self.0
87    }
88}
89#[doc = "Field `MEMO_INTR1` writer - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_1) while it in deep sleep or shut down mode"]
90pub struct MEMO_INTR1_W<'a> {
91    w: &'a mut W,
92}
93impl<'a> MEMO_INTR1_W<'a> {
94    #[doc = r"Sets the field bit"]
95    #[inline(always)]
96    pub fn set_bit(self) -> &'a mut W {
97        self.bit(true)
98    }
99    #[doc = r"Clears the field bit"]
100    #[inline(always)]
101    pub fn clear_bit(self) -> &'a mut W {
102        self.bit(false)
103    }
104    #[doc = r"Writes raw bits to the field"]
105    #[inline(always)]
106    pub fn bit(self, value: bool) -> &'a mut W {
107        self.w.bits =
108            (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
109        self.w
110    }
111}
112#[doc = "Field `MEMO_INTR2` reader - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_2) while it in deep sleep or shut down mode"]
113pub struct MEMO_INTR2_R(crate::FieldReader<bool, bool>);
114impl MEMO_INTR2_R {
115    #[inline(always)]
116    pub(crate) fn new(bits: bool) -> Self {
117        MEMO_INTR2_R(crate::FieldReader::new(bits))
118    }
119}
120impl core::ops::Deref for MEMO_INTR2_R {
121    type Target = crate::FieldReader<bool, bool>;
122    #[inline(always)]
123    fn deref(&self) -> &Self::Target {
124        &self.0
125    }
126}
127#[doc = "Field `MEMO_INTR2` writer - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_2) while it in deep sleep or shut down mode"]
128pub struct MEMO_INTR2_W<'a> {
129    w: &'a mut W,
130}
131impl<'a> MEMO_INTR2_W<'a> {
132    #[doc = r"Sets the field bit"]
133    #[inline(always)]
134    pub fn set_bit(self) -> &'a mut W {
135        self.bit(true)
136    }
137    #[doc = r"Clears the field bit"]
138    #[inline(always)]
139    pub fn clear_bit(self) -> &'a mut W {
140        self.bit(false)
141    }
142    #[doc = r"Writes raw bits to the field"]
143    #[inline(always)]
144    pub fn bit(self, value: bool) -> &'a mut W {
145        self.w.bits =
146            (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
147        self.w
148    }
149}
150#[doc = "Field `MEMO_INTR3` reader - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_3) while it in deep sleep or shut down mode"]
151pub struct MEMO_INTR3_R(crate::FieldReader<bool, bool>);
152impl MEMO_INTR3_R {
153    #[inline(always)]
154    pub(crate) fn new(bits: bool) -> Self {
155        MEMO_INTR3_R(crate::FieldReader::new(bits))
156    }
157}
158impl core::ops::Deref for MEMO_INTR3_R {
159    type Target = crate::FieldReader<bool, bool>;
160    #[inline(always)]
161    fn deref(&self) -> &Self::Target {
162        &self.0
163    }
164}
165#[doc = "Field `MEMO_INTR3` writer - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_3) while it in deep sleep or shut down mode"]
166pub struct MEMO_INTR3_W<'a> {
167    w: &'a mut W,
168}
169impl<'a> MEMO_INTR3_W<'a> {
170    #[doc = r"Sets the field bit"]
171    #[inline(always)]
172    pub fn set_bit(self) -> &'a mut W {
173        self.bit(true)
174    }
175    #[doc = r"Clears the field bit"]
176    #[inline(always)]
177    pub fn clear_bit(self) -> &'a mut W {
178        self.bit(false)
179    }
180    #[doc = r"Writes raw bits to the field"]
181    #[inline(always)]
182    pub fn bit(self, value: bool) -> &'a mut W {
183        self.w.bits =
184            (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
185        self.w
186    }
187}
188#[doc = "Field `MEM1_INTR0` reader - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_0) while it in deep sleep or shut down mode"]
189pub struct MEM1_INTR0_R(crate::FieldReader<bool, bool>);
190impl MEM1_INTR0_R {
191    #[inline(always)]
192    pub(crate) fn new(bits: bool) -> Self {
193        MEM1_INTR0_R(crate::FieldReader::new(bits))
194    }
195}
196impl core::ops::Deref for MEM1_INTR0_R {
197    type Target = crate::FieldReader<bool, bool>;
198    #[inline(always)]
199    fn deref(&self) -> &Self::Target {
200        &self.0
201    }
202}
203#[doc = "Field `MEM1_INTR0` writer - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_0) while it in deep sleep or shut down mode"]
204pub struct MEM1_INTR0_W<'a> {
205    w: &'a mut W,
206}
207impl<'a> MEM1_INTR0_W<'a> {
208    #[doc = r"Sets the field bit"]
209    #[inline(always)]
210    pub fn set_bit(self) -> &'a mut W {
211        self.bit(true)
212    }
213    #[doc = r"Clears the field bit"]
214    #[inline(always)]
215    pub fn clear_bit(self) -> &'a mut W {
216        self.bit(false)
217    }
218    #[doc = r"Writes raw bits to the field"]
219    #[inline(always)]
220    pub fn bit(self, value: bool) -> &'a mut W {
221        self.w.bits =
222            (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
223        self.w
224    }
225}
226#[doc = "Field `MEM1_INTR1` reader - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_1) while it in deep sleep or shut down mode"]
227pub struct MEM1_INTR1_R(crate::FieldReader<bool, bool>);
228impl MEM1_INTR1_R {
229    #[inline(always)]
230    pub(crate) fn new(bits: bool) -> Self {
231        MEM1_INTR1_R(crate::FieldReader::new(bits))
232    }
233}
234impl core::ops::Deref for MEM1_INTR1_R {
235    type Target = crate::FieldReader<bool, bool>;
236    #[inline(always)]
237    fn deref(&self) -> &Self::Target {
238        &self.0
239    }
240}
241#[doc = "Field `MEM1_INTR1` writer - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_1) while it in deep sleep or shut down mode"]
242pub struct MEM1_INTR1_W<'a> {
243    w: &'a mut W,
244}
245impl<'a> MEM1_INTR1_W<'a> {
246    #[doc = r"Sets the field bit"]
247    #[inline(always)]
248    pub fn set_bit(self) -> &'a mut W {
249        self.bit(true)
250    }
251    #[doc = r"Clears the field bit"]
252    #[inline(always)]
253    pub fn clear_bit(self) -> &'a mut W {
254        self.bit(false)
255    }
256    #[doc = r"Writes raw bits to the field"]
257    #[inline(always)]
258    pub fn bit(self, value: bool) -> &'a mut W {
259        self.w.bits =
260            (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
261        self.w
262    }
263}
264#[doc = "Field `MEM1_INTR2` reader - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_2) while it in deep sleep or shut down mode"]
265pub struct MEM1_INTR2_R(crate::FieldReader<bool, bool>);
266impl MEM1_INTR2_R {
267    #[inline(always)]
268    pub(crate) fn new(bits: bool) -> Self {
269        MEM1_INTR2_R(crate::FieldReader::new(bits))
270    }
271}
272impl core::ops::Deref for MEM1_INTR2_R {
273    type Target = crate::FieldReader<bool, bool>;
274    #[inline(always)]
275    fn deref(&self) -> &Self::Target {
276        &self.0
277    }
278}
279#[doc = "Field `MEM1_INTR2` writer - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_2) while it in deep sleep or shut down mode"]
280pub struct MEM1_INTR2_W<'a> {
281    w: &'a mut W,
282}
283impl<'a> MEM1_INTR2_W<'a> {
284    #[doc = r"Sets the field bit"]
285    #[inline(always)]
286    pub fn set_bit(self) -> &'a mut W {
287        self.bit(true)
288    }
289    #[doc = r"Clears the field bit"]
290    #[inline(always)]
291    pub fn clear_bit(self) -> &'a mut W {
292        self.bit(false)
293    }
294    #[doc = r"Writes raw bits to the field"]
295    #[inline(always)]
296    pub fn bit(self, value: bool) -> &'a mut W {
297        self.w.bits =
298            (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
299        self.w
300    }
301}
302#[doc = "Field `MEM1_INTR3` reader - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_3) while it in deep sleep or shut down mode"]
303pub struct MEM1_INTR3_R(crate::FieldReader<bool, bool>);
304impl MEM1_INTR3_R {
305    #[inline(always)]
306    pub(crate) fn new(bits: bool) -> Self {
307        MEM1_INTR3_R(crate::FieldReader::new(bits))
308    }
309}
310impl core::ops::Deref for MEM1_INTR3_R {
311    type Target = crate::FieldReader<bool, bool>;
312    #[inline(always)]
313    fn deref(&self) -> &Self::Target {
314        &self.0
315    }
316}
317#[doc = "Field `MEM1_INTR3` writer - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_3) while it in deep sleep or shut down mode"]
318pub struct MEM1_INTR3_W<'a> {
319    w: &'a mut W,
320}
321impl<'a> MEM1_INTR3_W<'a> {
322    #[doc = r"Sets the field bit"]
323    #[inline(always)]
324    pub fn set_bit(self) -> &'a mut W {
325        self.bit(true)
326    }
327    #[doc = r"Clears the field bit"]
328    #[inline(always)]
329    pub fn clear_bit(self) -> &'a mut W {
330        self.bit(false)
331    }
332    #[doc = r"Writes raw bits to the field"]
333    #[inline(always)]
334    pub fn bit(self, value: bool) -> &'a mut W {
335        self.w.bits =
336            (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
337        self.w
338    }
339}
340#[doc = "Field `MEM2_INTR0` reader - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_0) while it in deep sleep or shut down mode"]
341pub struct MEM2_INTR0_R(crate::FieldReader<bool, bool>);
342impl MEM2_INTR0_R {
343    #[inline(always)]
344    pub(crate) fn new(bits: bool) -> Self {
345        MEM2_INTR0_R(crate::FieldReader::new(bits))
346    }
347}
348impl core::ops::Deref for MEM2_INTR0_R {
349    type Target = crate::FieldReader<bool, bool>;
350    #[inline(always)]
351    fn deref(&self) -> &Self::Target {
352        &self.0
353    }
354}
355#[doc = "Field `MEM2_INTR0` writer - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_0) while it in deep sleep or shut down mode"]
356pub struct MEM2_INTR0_W<'a> {
357    w: &'a mut W,
358}
359impl<'a> MEM2_INTR0_W<'a> {
360    #[doc = r"Sets the field bit"]
361    #[inline(always)]
362    pub fn set_bit(self) -> &'a mut W {
363        self.bit(true)
364    }
365    #[doc = r"Clears the field bit"]
366    #[inline(always)]
367    pub fn clear_bit(self) -> &'a mut W {
368        self.bit(false)
369    }
370    #[doc = r"Writes raw bits to the field"]
371    #[inline(always)]
372    pub fn bit(self, value: bool) -> &'a mut W {
373        self.w.bits =
374            (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
375        self.w
376    }
377}
378#[doc = "Field `MEM2_INTR1` reader - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_1) while it in deep sleep or shut down mode"]
379pub struct MEM2_INTR1_R(crate::FieldReader<bool, bool>);
380impl MEM2_INTR1_R {
381    #[inline(always)]
382    pub(crate) fn new(bits: bool) -> Self {
383        MEM2_INTR1_R(crate::FieldReader::new(bits))
384    }
385}
386impl core::ops::Deref for MEM2_INTR1_R {
387    type Target = crate::FieldReader<bool, bool>;
388    #[inline(always)]
389    fn deref(&self) -> &Self::Target {
390        &self.0
391    }
392}
393#[doc = "Field `MEM2_INTR1` writer - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_1) while it in deep sleep or shut down mode"]
394pub struct MEM2_INTR1_W<'a> {
395    w: &'a mut W,
396}
397impl<'a> MEM2_INTR1_W<'a> {
398    #[doc = r"Sets the field bit"]
399    #[inline(always)]
400    pub fn set_bit(self) -> &'a mut W {
401        self.bit(true)
402    }
403    #[doc = r"Clears the field bit"]
404    #[inline(always)]
405    pub fn clear_bit(self) -> &'a mut W {
406        self.bit(false)
407    }
408    #[doc = r"Writes raw bits to the field"]
409    #[inline(always)]
410    pub fn bit(self, value: bool) -> &'a mut W {
411        self.w.bits =
412            (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
413        self.w
414    }
415}
416#[doc = "Field `MEM2_INTR2` reader - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_2) while it in deep sleep or shut down mode"]
417pub struct MEM2_INTR2_R(crate::FieldReader<bool, bool>);
418impl MEM2_INTR2_R {
419    #[inline(always)]
420    pub(crate) fn new(bits: bool) -> Self {
421        MEM2_INTR2_R(crate::FieldReader::new(bits))
422    }
423}
424impl core::ops::Deref for MEM2_INTR2_R {
425    type Target = crate::FieldReader<bool, bool>;
426    #[inline(always)]
427    fn deref(&self) -> &Self::Target {
428        &self.0
429    }
430}
431#[doc = "Field `MEM2_INTR2` writer - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_2) while it in deep sleep or shut down mode"]
432pub struct MEM2_INTR2_W<'a> {
433    w: &'a mut W,
434}
435impl<'a> MEM2_INTR2_W<'a> {
436    #[doc = r"Sets the field bit"]
437    #[inline(always)]
438    pub fn set_bit(self) -> &'a mut W {
439        self.bit(true)
440    }
441    #[doc = r"Clears the field bit"]
442    #[inline(always)]
443    pub fn clear_bit(self) -> &'a mut W {
444        self.bit(false)
445    }
446    #[doc = r"Writes raw bits to the field"]
447    #[inline(always)]
448    pub fn bit(self, value: bool) -> &'a mut W {
449        self.w.bits =
450            (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
451        self.w
452    }
453}
454#[doc = "Field `MEM2_INTR3` reader - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_3) while it in deep sleep or shut down mode"]
455pub struct MEM2_INTR3_R(crate::FieldReader<bool, bool>);
456impl MEM2_INTR3_R {
457    #[inline(always)]
458    pub(crate) fn new(bits: bool) -> Self {
459        MEM2_INTR3_R(crate::FieldReader::new(bits))
460    }
461}
462impl core::ops::Deref for MEM2_INTR3_R {
463    type Target = crate::FieldReader<bool, bool>;
464    #[inline(always)]
465    fn deref(&self) -> &Self::Target {
466        &self.0
467    }
468}
469#[doc = "Field `MEM2_INTR3` writer - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_3) while it in deep sleep or shut down mode"]
470pub struct MEM2_INTR3_W<'a> {
471    w: &'a mut W,
472}
473impl<'a> MEM2_INTR3_W<'a> {
474    #[doc = r"Sets the field bit"]
475    #[inline(always)]
476    pub fn set_bit(self) -> &'a mut W {
477        self.bit(true)
478    }
479    #[doc = r"Clears the field bit"]
480    #[inline(always)]
481    pub fn clear_bit(self) -> &'a mut W {
482        self.bit(false)
483    }
484    #[doc = r"Writes raw bits to the field"]
485    #[inline(always)]
486    pub fn bit(self, value: bool) -> &'a mut W {
487        self.w.bits =
488            (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
489        self.w
490    }
491}
492impl R {
493    #[doc = "Bit 0 - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_0) while it in deep sleep or shut down mode"]
494    #[inline(always)]
495    pub fn memo_intr0(&self) -> MEMO_INTR0_R {
496        MEMO_INTR0_R::new((self.bits & 0x01) != 0)
497    }
498    #[doc = "Bit 1 - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_1) while it in deep sleep or shut down mode"]
499    #[inline(always)]
500    pub fn memo_intr1(&self) -> MEMO_INTR1_R {
501        MEMO_INTR1_R::new(((self.bits >> 1) & 0x01) != 0)
502    }
503    #[doc = "Bit 2 - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_2) while it in deep sleep or shut down mode"]
504    #[inline(always)]
505    pub fn memo_intr2(&self) -> MEMO_INTR2_R {
506        MEMO_INTR2_R::new(((self.bits >> 2) & 0x01) != 0)
507    }
508    #[doc = "Bit 3 - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_3) while it in deep sleep or shut down mode"]
509    #[inline(always)]
510    pub fn memo_intr3(&self) -> MEMO_INTR3_R {
511        MEMO_INTR3_R::new(((self.bits >> 3) & 0x01) != 0)
512    }
513    #[doc = "Bit 4 - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_0) while it in deep sleep or shut down mode"]
514    #[inline(always)]
515    pub fn mem1_intr0(&self) -> MEM1_INTR0_R {
516        MEM1_INTR0_R::new(((self.bits >> 4) & 0x01) != 0)
517    }
518    #[doc = "Bit 5 - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_1) while it in deep sleep or shut down mode"]
519    #[inline(always)]
520    pub fn mem1_intr1(&self) -> MEM1_INTR1_R {
521        MEM1_INTR1_R::new(((self.bits >> 5) & 0x01) != 0)
522    }
523    #[doc = "Bit 6 - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_2) while it in deep sleep or shut down mode"]
524    #[inline(always)]
525    pub fn mem1_intr2(&self) -> MEM1_INTR2_R {
526        MEM1_INTR2_R::new(((self.bits >> 6) & 0x01) != 0)
527    }
528    #[doc = "Bit 7 - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_3) while it in deep sleep or shut down mode"]
529    #[inline(always)]
530    pub fn mem1_intr3(&self) -> MEM1_INTR3_R {
531        MEM1_INTR3_R::new(((self.bits >> 7) & 0x01) != 0)
532    }
533    #[doc = "Bit 8 - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_0) while it in deep sleep or shut down mode"]
534    #[inline(always)]
535    pub fn mem2_intr0(&self) -> MEM2_INTR0_R {
536        MEM2_INTR0_R::new(((self.bits >> 8) & 0x01) != 0)
537    }
538    #[doc = "Bit 9 - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_1) while it in deep sleep or shut down mode"]
539    #[inline(always)]
540    pub fn mem2_intr1(&self) -> MEM2_INTR1_R {
541        MEM2_INTR1_R::new(((self.bits >> 9) & 0x01) != 0)
542    }
543    #[doc = "Bit 10 - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_2) while it in deep sleep or shut down mode"]
544    #[inline(always)]
545    pub fn mem2_intr2(&self) -> MEM2_INTR2_R {
546        MEM2_INTR2_R::new(((self.bits >> 10) & 0x01) != 0)
547    }
548    #[doc = "Bit 11 - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_3) while it in deep sleep or shut down mode"]
549    #[inline(always)]
550    pub fn mem2_intr3(&self) -> MEM2_INTR3_R {
551        MEM2_INTR3_R::new(((self.bits >> 11) & 0x01) != 0)
552    }
553}
554impl W {
555    #[doc = "Bit 0 - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_0) while it in deep sleep or shut down mode"]
556    #[inline(always)]
557    pub fn memo_intr0(&mut self) -> MEMO_INTR0_W {
558        MEMO_INTR0_W { w: self }
559    }
560    #[doc = "Bit 1 - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_1) while it in deep sleep or shut down mode"]
561    #[inline(always)]
562    pub fn memo_intr1(&mut self) -> MEMO_INTR1_W {
563        MEMO_INTR1_W { w: self }
564    }
565    #[doc = "Bit 2 - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_2) while it in deep sleep or shut down mode"]
566    #[inline(always)]
567    pub fn memo_intr2(&mut self) -> MEMO_INTR2_W {
568        MEMO_INTR2_W { w: self }
569    }
570    #[doc = "Bit 3 - Interrupt caused by a SRAM access (M4 SRAM segment 0 32KB_3) while it in deep sleep or shut down mode"]
571    #[inline(always)]
572    pub fn memo_intr3(&mut self) -> MEMO_INTR3_W {
573        MEMO_INTR3_W { w: self }
574    }
575    #[doc = "Bit 4 - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_0) while it in deep sleep or shut down mode"]
576    #[inline(always)]
577    pub fn mem1_intr0(&mut self) -> MEM1_INTR0_W {
578        MEM1_INTR0_W { w: self }
579    }
580    #[doc = "Bit 5 - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_1) while it in deep sleep or shut down mode"]
581    #[inline(always)]
582    pub fn mem1_intr1(&mut self) -> MEM1_INTR1_W {
583        MEM1_INTR1_W { w: self }
584    }
585    #[doc = "Bit 6 - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_2) while it in deep sleep or shut down mode"]
586    #[inline(always)]
587    pub fn mem1_intr2(&mut self) -> MEM1_INTR2_W {
588        MEM1_INTR2_W { w: self }
589    }
590    #[doc = "Bit 7 - Interrupt caused by a SRAM access (M4 SRAM segment 1 32KB_3) while it in deep sleep or shut down mode"]
591    #[inline(always)]
592    pub fn mem1_intr3(&mut self) -> MEM1_INTR3_W {
593        MEM1_INTR3_W { w: self }
594    }
595    #[doc = "Bit 8 - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_0) while it in deep sleep or shut down mode"]
596    #[inline(always)]
597    pub fn mem2_intr0(&mut self) -> MEM2_INTR0_W {
598        MEM2_INTR0_W { w: self }
599    }
600    #[doc = "Bit 9 - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_1) while it in deep sleep or shut down mode"]
601    #[inline(always)]
602    pub fn mem2_intr1(&mut self) -> MEM2_INTR1_W {
603        MEM2_INTR1_W { w: self }
604    }
605    #[doc = "Bit 10 - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_2) while it in deep sleep or shut down mode"]
606    #[inline(always)]
607    pub fn mem2_intr2(&mut self) -> MEM2_INTR2_W {
608        MEM2_INTR2_W { w: self }
609    }
610    #[doc = "Bit 11 - Interrupt caused by a SRAM access (M4 SRAM segment 2 32KB_3) while it in deep sleep or shut down mode"]
611    #[inline(always)]
612    pub fn mem2_intr3(&mut self) -> MEM2_INTR3_W {
613        MEM2_INTR3_W { w: self }
614    }
615    #[doc = "Writes raw bits to the register."]
616    #[inline(always)]
617    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
618        self.0.bits(bits);
619        self
620    }
621}
622#[doc = "SRAM access while in low power mode interrupt flag register (Set bit to clear)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [m4_mem_int](index.html) module"]
623pub struct M4_MEM_INT_SPEC;
624impl crate::RegisterSpec for M4_MEM_INT_SPEC {
625    type Ux = u32;
626}
627#[doc = "`read()` method returns [m4_mem_int::R](R) reader structure"]
628impl crate::Readable for M4_MEM_INT_SPEC {
629    type Reader = R;
630}
631#[doc = "`write(|w| ..)` method takes [m4_mem_int::W](W) writer structure"]
632impl crate::Writable for M4_MEM_INT_SPEC {
633    type Writer = W;
634}
635#[doc = "`reset()` method sets M4_MEM_INT to value 0"]
636impl crate::Resettable for M4_MEM_INT_SPEC {
637    #[inline(always)]
638    fn reset_value() -> Self::Ux {
639        0
640    }
641}
eos_s3/extm4regs/m4_mem_int.rs

eos_s3/extm4regs/
m4_mem_int.rs
