eos_s3/ext_regs_ffe/
interrupt_en.rs

1#[doc = "Register `INTERRUPT_EN` reader"]
2pub struct R(crate::R<INTERRUPT_EN_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<INTERRUPT_EN_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<INTERRUPT_EN_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<INTERRUPT_EN_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `INTERRUPT_EN` writer"]
17pub struct W(crate::W<INTERRUPT_EN_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<INTERRUPT_EN_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<INTERRUPT_EN_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<INTERRUPT_EN_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Set to enable the interrupt, leave cleared to mask\n\nValue on reset: 0"]
38#[derive(Clone, Copy, Debug, PartialEq)]
39pub enum SM_MULT_WR_INTR_EN_A {
40    #[doc = "0: Mask the interrupt event"]
41    MASK = 0,
42    #[doc = "1: Unmask the interrupt event"]
43    UNMASK = 1,
44}
45impl From<SM_MULT_WR_INTR_EN_A> for bool {
46    #[inline(always)]
47    fn from(variant: SM_MULT_WR_INTR_EN_A) -> Self {
48        variant as u8 != 0
49    }
50}
51#[doc = "Field `SM_MULT_WR_INTR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
52pub struct SM_MULT_WR_INTR_EN_R(crate::FieldReader<bool, SM_MULT_WR_INTR_EN_A>);
53impl SM_MULT_WR_INTR_EN_R {
54    #[inline(always)]
55    pub(crate) fn new(bits: bool) -> Self {
56        SM_MULT_WR_INTR_EN_R(crate::FieldReader::new(bits))
57    }
58    #[doc = r"Get enumerated values variant"]
59    #[inline(always)]
60    pub fn variant(&self) -> SM_MULT_WR_INTR_EN_A {
61        match self.bits {
62            false => SM_MULT_WR_INTR_EN_A::MASK,
63            true => SM_MULT_WR_INTR_EN_A::UNMASK,
64        }
65    }
66    #[doc = "Checks if the value of the field is `MASK`"]
67    #[inline(always)]
68    pub fn is_mask(&self) -> bool {
69        **self == SM_MULT_WR_INTR_EN_A::MASK
70    }
71    #[doc = "Checks if the value of the field is `UNMASK`"]
72    #[inline(always)]
73    pub fn is_unmask(&self) -> bool {
74        **self == SM_MULT_WR_INTR_EN_A::UNMASK
75    }
76}
77impl core::ops::Deref for SM_MULT_WR_INTR_EN_R {
78    type Target = crate::FieldReader<bool, SM_MULT_WR_INTR_EN_A>;
79    #[inline(always)]
80    fn deref(&self) -> &Self::Target {
81        &self.0
82    }
83}
84#[doc = "Field `SM_MULT_WR_INTR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
85pub struct SM_MULT_WR_INTR_EN_W<'a> {
86    w: &'a mut W,
87}
88impl<'a> SM_MULT_WR_INTR_EN_W<'a> {
89    #[doc = r"Writes `variant` to the field"]
90    #[inline(always)]
91    pub fn variant(self, variant: SM_MULT_WR_INTR_EN_A) -> &'a mut W {
92        self.bit(variant.into())
93    }
94    #[doc = "Mask the interrupt event"]
95    #[inline(always)]
96    pub fn mask(self) -> &'a mut W {
97        self.variant(SM_MULT_WR_INTR_EN_A::MASK)
98    }
99    #[doc = "Unmask the interrupt event"]
100    #[inline(always)]
101    pub fn unmask(self) -> &'a mut W {
102        self.variant(SM_MULT_WR_INTR_EN_A::UNMASK)
103    }
104    #[doc = r"Sets the field bit"]
105    #[inline(always)]
106    pub fn set_bit(self) -> &'a mut W {
107        self.bit(true)
108    }
109    #[doc = r"Clears the field bit"]
110    #[inline(always)]
111    pub fn clear_bit(self) -> &'a mut W {
112        self.bit(false)
113    }
114    #[doc = r"Writes raw bits to the field"]
115    #[inline(always)]
116    pub fn bit(self, value: bool) -> &'a mut W {
117        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
118        self.w
119    }
120}
121#[doc = "Set to enable the interrupt, leave cleared to mask"]
122pub type FFE0_OVERRUN_EN_A = SM_MULT_WR_INTR_EN_A;
123#[doc = "Field `FFE0_OVERRUN_EN` reader - Set to enable the interrupt, leave cleared to mask"]
124pub type FFE0_OVERRUN_EN_R = SM_MULT_WR_INTR_EN_R;
125#[doc = "Field `FFE0_OVERRUN_EN` writer - Set to enable the interrupt, leave cleared to mask"]
126pub struct FFE0_OVERRUN_EN_W<'a> {
127    w: &'a mut W,
128}
129impl<'a> FFE0_OVERRUN_EN_W<'a> {
130    #[doc = r"Writes `variant` to the field"]
131    #[inline(always)]
132    pub fn variant(self, variant: FFE0_OVERRUN_EN_A) -> &'a mut W {
133        self.bit(variant.into())
134    }
135    #[doc = "Mask the interrupt event"]
136    #[inline(always)]
137    pub fn mask(self) -> &'a mut W {
138        self.variant(FFE0_OVERRUN_EN_A::MASK)
139    }
140    #[doc = "Unmask the interrupt event"]
141    #[inline(always)]
142    pub fn unmask(self) -> &'a mut W {
143        self.variant(FFE0_OVERRUN_EN_A::UNMASK)
144    }
145    #[doc = r"Sets the field bit"]
146    #[inline(always)]
147    pub fn set_bit(self) -> &'a mut W {
148        self.bit(true)
149    }
150    #[doc = r"Clears the field bit"]
151    #[inline(always)]
152    pub fn clear_bit(self) -> &'a mut W {
153        self.bit(false)
154    }
155    #[doc = r"Writes raw bits to the field"]
156    #[inline(always)]
157    pub fn bit(self, value: bool) -> &'a mut W {
158        self.w.bits =
159            (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
160        self.w
161    }
162}
163#[doc = "Set to enable the interrupt, leave cleared to mask"]
164pub type FFE0_SM1_OVERRUN_EN_A = SM_MULT_WR_INTR_EN_A;
165#[doc = "Field `FFE0_SM1_OVERRUN_EN` reader - Set to enable the interrupt, leave cleared to mask"]
166pub type FFE0_SM1_OVERRUN_EN_R = SM_MULT_WR_INTR_EN_R;
167#[doc = "Field `FFE0_SM1_OVERRUN_EN` writer - Set to enable the interrupt, leave cleared to mask"]
168pub struct FFE0_SM1_OVERRUN_EN_W<'a> {
169    w: &'a mut W,
170}
171impl<'a> FFE0_SM1_OVERRUN_EN_W<'a> {
172    #[doc = r"Writes `variant` to the field"]
173    #[inline(always)]
174    pub fn variant(self, variant: FFE0_SM1_OVERRUN_EN_A) -> &'a mut W {
175        self.bit(variant.into())
176    }
177    #[doc = "Mask the interrupt event"]
178    #[inline(always)]
179    pub fn mask(self) -> &'a mut W {
180        self.variant(FFE0_SM1_OVERRUN_EN_A::MASK)
181    }
182    #[doc = "Unmask the interrupt event"]
183    #[inline(always)]
184    pub fn unmask(self) -> &'a mut W {
185        self.variant(FFE0_SM1_OVERRUN_EN_A::UNMASK)
186    }
187    #[doc = r"Sets the field bit"]
188    #[inline(always)]
189    pub fn set_bit(self) -> &'a mut W {
190        self.bit(true)
191    }
192    #[doc = r"Clears the field bit"]
193    #[inline(always)]
194    pub fn clear_bit(self) -> &'a mut W {
195        self.bit(false)
196    }
197    #[doc = r"Writes raw bits to the field"]
198    #[inline(always)]
199    pub fn bit(self, value: bool) -> &'a mut W {
200        self.w.bits =
201            (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
202        self.w
203    }
204}
205#[doc = "Set to enable the interrupt, leave cleared to mask"]
206pub type FFE0_SM0_OVERRUN_EN_A = SM_MULT_WR_INTR_EN_A;
207#[doc = "Field `FFE0_SM0_OVERRUN_EN` reader - Set to enable the interrupt, leave cleared to mask"]
208pub type FFE0_SM0_OVERRUN_EN_R = SM_MULT_WR_INTR_EN_R;
209#[doc = "Field `FFE0_SM0_OVERRUN_EN` writer - Set to enable the interrupt, leave cleared to mask"]
210pub struct FFE0_SM0_OVERRUN_EN_W<'a> {
211    w: &'a mut W,
212}
213impl<'a> FFE0_SM0_OVERRUN_EN_W<'a> {
214    #[doc = r"Writes `variant` to the field"]
215    #[inline(always)]
216    pub fn variant(self, variant: FFE0_SM0_OVERRUN_EN_A) -> &'a mut W {
217        self.bit(variant.into())
218    }
219    #[doc = "Mask the interrupt event"]
220    #[inline(always)]
221    pub fn mask(self) -> &'a mut W {
222        self.variant(FFE0_SM0_OVERRUN_EN_A::MASK)
223    }
224    #[doc = "Unmask the interrupt event"]
225    #[inline(always)]
226    pub fn unmask(self) -> &'a mut W {
227        self.variant(FFE0_SM0_OVERRUN_EN_A::UNMASK)
228    }
229    #[doc = r"Sets the field bit"]
230    #[inline(always)]
231    pub fn set_bit(self) -> &'a mut W {
232        self.bit(true)
233    }
234    #[doc = r"Clears the field bit"]
235    #[inline(always)]
236    pub fn clear_bit(self) -> &'a mut W {
237        self.bit(false)
238    }
239    #[doc = r"Writes raw bits to the field"]
240    #[inline(always)]
241    pub fn bit(self, value: bool) -> &'a mut W {
242        self.w.bits =
243            (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
244        self.w
245    }
246}
247#[doc = "Set to enable the interrupt, leave cleared to mask"]
248pub type I2C_MS_1_ERROR_EN_A = SM_MULT_WR_INTR_EN_A;
249#[doc = "Field `I2C_MS_1_ERROR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
250pub type I2C_MS_1_ERROR_EN_R = SM_MULT_WR_INTR_EN_R;
251#[doc = "Field `I2C_MS_1_ERROR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
252pub struct I2C_MS_1_ERROR_EN_W<'a> {
253    w: &'a mut W,
254}
255impl<'a> I2C_MS_1_ERROR_EN_W<'a> {
256    #[doc = r"Writes `variant` to the field"]
257    #[inline(always)]
258    pub fn variant(self, variant: I2C_MS_1_ERROR_EN_A) -> &'a mut W {
259        self.bit(variant.into())
260    }
261    #[doc = "Mask the interrupt event"]
262    #[inline(always)]
263    pub fn mask(self) -> &'a mut W {
264        self.variant(I2C_MS_1_ERROR_EN_A::MASK)
265    }
266    #[doc = "Unmask the interrupt event"]
267    #[inline(always)]
268    pub fn unmask(self) -> &'a mut W {
269        self.variant(I2C_MS_1_ERROR_EN_A::UNMASK)
270    }
271    #[doc = r"Sets the field bit"]
272    #[inline(always)]
273    pub fn set_bit(self) -> &'a mut W {
274        self.bit(true)
275    }
276    #[doc = r"Clears the field bit"]
277    #[inline(always)]
278    pub fn clear_bit(self) -> &'a mut W {
279        self.bit(false)
280    }
281    #[doc = r"Writes raw bits to the field"]
282    #[inline(always)]
283    pub fn bit(self, value: bool) -> &'a mut W {
284        self.w.bits =
285            (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
286        self.w
287    }
288}
289#[doc = "Set to enable the interrupt, leave cleared to mask"]
290pub type I2C_MS_0_ERROR_EN_A = SM_MULT_WR_INTR_EN_A;
291#[doc = "Field `I2C_MS_0_ERROR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
292pub type I2C_MS_0_ERROR_EN_R = SM_MULT_WR_INTR_EN_R;
293#[doc = "Field `I2C_MS_0_ERROR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
294pub struct I2C_MS_0_ERROR_EN_W<'a> {
295    w: &'a mut W,
296}
297impl<'a> I2C_MS_0_ERROR_EN_W<'a> {
298    #[doc = r"Writes `variant` to the field"]
299    #[inline(always)]
300    pub fn variant(self, variant: I2C_MS_0_ERROR_EN_A) -> &'a mut W {
301        self.bit(variant.into())
302    }
303    #[doc = "Mask the interrupt event"]
304    #[inline(always)]
305    pub fn mask(self) -> &'a mut W {
306        self.variant(I2C_MS_0_ERROR_EN_A::MASK)
307    }
308    #[doc = "Unmask the interrupt event"]
309    #[inline(always)]
310    pub fn unmask(self) -> &'a mut W {
311        self.variant(I2C_MS_0_ERROR_EN_A::UNMASK)
312    }
313    #[doc = r"Sets the field bit"]
314    #[inline(always)]
315    pub fn set_bit(self) -> &'a mut W {
316        self.bit(true)
317    }
318    #[doc = r"Clears the field bit"]
319    #[inline(always)]
320    pub fn clear_bit(self) -> &'a mut W {
321        self.bit(false)
322    }
323    #[doc = r"Writes raw bits to the field"]
324    #[inline(always)]
325    pub fn bit(self, value: bool) -> &'a mut W {
326        self.w.bits =
327            (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
328        self.w
329    }
330}
331#[doc = "Set to enable the interrupt, leave cleared to mask"]
332pub type CM_8K_LP_INTR_EN_A = SM_MULT_WR_INTR_EN_A;
333#[doc = "Field `CM_8k_LP_INTR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
334pub type CM_8K_LP_INTR_EN_R = SM_MULT_WR_INTR_EN_R;
335#[doc = "Field `CM_8k_LP_INTR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
336pub struct CM_8K_LP_INTR_EN_W<'a> {
337    w: &'a mut W,
338}
339impl<'a> CM_8K_LP_INTR_EN_W<'a> {
340    #[doc = r"Writes `variant` to the field"]
341    #[inline(always)]
342    pub fn variant(self, variant: CM_8K_LP_INTR_EN_A) -> &'a mut W {
343        self.bit(variant.into())
344    }
345    #[doc = "Mask the interrupt event"]
346    #[inline(always)]
347    pub fn mask(self) -> &'a mut W {
348        self.variant(CM_8K_LP_INTR_EN_A::MASK)
349    }
350    #[doc = "Unmask the interrupt event"]
351    #[inline(always)]
352    pub fn unmask(self) -> &'a mut W {
353        self.variant(CM_8K_LP_INTR_EN_A::UNMASK)
354    }
355    #[doc = r"Sets the field bit"]
356    #[inline(always)]
357    pub fn set_bit(self) -> &'a mut W {
358        self.bit(true)
359    }
360    #[doc = r"Clears the field bit"]
361    #[inline(always)]
362    pub fn clear_bit(self) -> &'a mut W {
363        self.bit(false)
364    }
365    #[doc = r"Writes raw bits to the field"]
366    #[inline(always)]
367    pub fn bit(self, value: bool) -> &'a mut W {
368        self.w.bits =
369            (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
370        self.w
371    }
372}
373#[doc = "Set to enable the interrupt, leave cleared to mask"]
374pub type DM0_LP_INTR_EN_A = SM_MULT_WR_INTR_EN_A;
375#[doc = "Field `DM0_LP_INTR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
376pub type DM0_LP_INTR_EN_R = SM_MULT_WR_INTR_EN_R;
377#[doc = "Field `DM0_LP_INTR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
378pub struct DM0_LP_INTR_EN_W<'a> {
379    w: &'a mut W,
380}
381impl<'a> DM0_LP_INTR_EN_W<'a> {
382    #[doc = r"Writes `variant` to the field"]
383    #[inline(always)]
384    pub fn variant(self, variant: DM0_LP_INTR_EN_A) -> &'a mut W {
385        self.bit(variant.into())
386    }
387    #[doc = "Mask the interrupt event"]
388    #[inline(always)]
389    pub fn mask(self) -> &'a mut W {
390        self.variant(DM0_LP_INTR_EN_A::MASK)
391    }
392    #[doc = "Unmask the interrupt event"]
393    #[inline(always)]
394    pub fn unmask(self) -> &'a mut W {
395        self.variant(DM0_LP_INTR_EN_A::UNMASK)
396    }
397    #[doc = r"Sets the field bit"]
398    #[inline(always)]
399    pub fn set_bit(self) -> &'a mut W {
400        self.bit(true)
401    }
402    #[doc = r"Clears the field bit"]
403    #[inline(always)]
404    pub fn clear_bit(self) -> &'a mut W {
405        self.bit(false)
406    }
407    #[doc = r"Writes raw bits to the field"]
408    #[inline(always)]
409    pub fn bit(self, value: bool) -> &'a mut W {
410        self.w.bits =
411            (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
412        self.w
413    }
414}
415#[doc = "Set to enable the interrupt, leave cleared to mask"]
416pub type DM1_LP_INTR_EN_A = SM_MULT_WR_INTR_EN_A;
417#[doc = "Field `DM1_LP_INTR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
418pub type DM1_LP_INTR_EN_R = SM_MULT_WR_INTR_EN_R;
419#[doc = "Field `DM1_LP_INTR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
420pub struct DM1_LP_INTR_EN_W<'a> {
421    w: &'a mut W,
422}
423impl<'a> DM1_LP_INTR_EN_W<'a> {
424    #[doc = r"Writes `variant` to the field"]
425    #[inline(always)]
426    pub fn variant(self, variant: DM1_LP_INTR_EN_A) -> &'a mut W {
427        self.bit(variant.into())
428    }
429    #[doc = "Mask the interrupt event"]
430    #[inline(always)]
431    pub fn mask(self) -> &'a mut W {
432        self.variant(DM1_LP_INTR_EN_A::MASK)
433    }
434    #[doc = "Unmask the interrupt event"]
435    #[inline(always)]
436    pub fn unmask(self) -> &'a mut W {
437        self.variant(DM1_LP_INTR_EN_A::UNMASK)
438    }
439    #[doc = r"Sets the field bit"]
440    #[inline(always)]
441    pub fn set_bit(self) -> &'a mut W {
442        self.bit(true)
443    }
444    #[doc = r"Clears the field bit"]
445    #[inline(always)]
446    pub fn clear_bit(self) -> &'a mut W {
447        self.bit(false)
448    }
449    #[doc = r"Writes raw bits to the field"]
450    #[inline(always)]
451    pub fn bit(self, value: bool) -> &'a mut W {
452        self.w.bits =
453            (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
454        self.w
455    }
456}
457#[doc = "Set to enable the interrupt, leave cleared to mask"]
458pub type SM0_LP_INTR_EN_A = SM_MULT_WR_INTR_EN_A;
459#[doc = "Field `SM0_LP_INTR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
460pub type SM0_LP_INTR_EN_R = SM_MULT_WR_INTR_EN_R;
461#[doc = "Field `SM0_LP_INTR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
462pub struct SM0_LP_INTR_EN_W<'a> {
463    w: &'a mut W,
464}
465impl<'a> SM0_LP_INTR_EN_W<'a> {
466    #[doc = r"Writes `variant` to the field"]
467    #[inline(always)]
468    pub fn variant(self, variant: SM0_LP_INTR_EN_A) -> &'a mut W {
469        self.bit(variant.into())
470    }
471    #[doc = "Mask the interrupt event"]
472    #[inline(always)]
473    pub fn mask(self) -> &'a mut W {
474        self.variant(SM0_LP_INTR_EN_A::MASK)
475    }
476    #[doc = "Unmask the interrupt event"]
477    #[inline(always)]
478    pub fn unmask(self) -> &'a mut W {
479        self.variant(SM0_LP_INTR_EN_A::UNMASK)
480    }
481    #[doc = r"Sets the field bit"]
482    #[inline(always)]
483    pub fn set_bit(self) -> &'a mut W {
484        self.bit(true)
485    }
486    #[doc = r"Clears the field bit"]
487    #[inline(always)]
488    pub fn clear_bit(self) -> &'a mut W {
489        self.bit(false)
490    }
491    #[doc = r"Writes raw bits to the field"]
492    #[inline(always)]
493    pub fn bit(self, value: bool) -> &'a mut W {
494        self.w.bits =
495            (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
496        self.w
497    }
498}
499#[doc = "Set to enable the interrupt, leave cleared to mask"]
500pub type SM1_LP_INTR_EN_A = SM_MULT_WR_INTR_EN_A;
501#[doc = "Field `SM1_LP_INTR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
502pub type SM1_LP_INTR_EN_R = SM_MULT_WR_INTR_EN_R;
503#[doc = "Field `SM1_LP_INTR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
504pub struct SM1_LP_INTR_EN_W<'a> {
505    w: &'a mut W,
506}
507impl<'a> SM1_LP_INTR_EN_W<'a> {
508    #[doc = r"Writes `variant` to the field"]
509    #[inline(always)]
510    pub fn variant(self, variant: SM1_LP_INTR_EN_A) -> &'a mut W {
511        self.bit(variant.into())
512    }
513    #[doc = "Mask the interrupt event"]
514    #[inline(always)]
515    pub fn mask(self) -> &'a mut W {
516        self.variant(SM1_LP_INTR_EN_A::MASK)
517    }
518    #[doc = "Unmask the interrupt event"]
519    #[inline(always)]
520    pub fn unmask(self) -> &'a mut W {
521        self.variant(SM1_LP_INTR_EN_A::UNMASK)
522    }
523    #[doc = r"Sets the field bit"]
524    #[inline(always)]
525    pub fn set_bit(self) -> &'a mut W {
526        self.bit(true)
527    }
528    #[doc = r"Clears the field bit"]
529    #[inline(always)]
530    pub fn clear_bit(self) -> &'a mut W {
531        self.bit(false)
532    }
533    #[doc = r"Writes raw bits to the field"]
534    #[inline(always)]
535    pub fn bit(self, value: bool) -> &'a mut W {
536        self.w.bits =
537            (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
538        self.w
539    }
540}
541#[doc = "Set to enable the interrupt, leave cleared to mask"]
542pub type FFE0_BP_MATCH_INTR_EN_A = SM_MULT_WR_INTR_EN_A;
543#[doc = "Field `FFE0_BP_MATCH_INTR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
544pub type FFE0_BP_MATCH_INTR_EN_R = SM_MULT_WR_INTR_EN_R;
545#[doc = "Field `FFE0_BP_MATCH_INTR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
546pub struct FFE0_BP_MATCH_INTR_EN_W<'a> {
547    w: &'a mut W,
548}
549impl<'a> FFE0_BP_MATCH_INTR_EN_W<'a> {
550    #[doc = r"Writes `variant` to the field"]
551    #[inline(always)]
552    pub fn variant(self, variant: FFE0_BP_MATCH_INTR_EN_A) -> &'a mut W {
553        self.bit(variant.into())
554    }
555    #[doc = "Mask the interrupt event"]
556    #[inline(always)]
557    pub fn mask(self) -> &'a mut W {
558        self.variant(FFE0_BP_MATCH_INTR_EN_A::MASK)
559    }
560    #[doc = "Unmask the interrupt event"]
561    #[inline(always)]
562    pub fn unmask(self) -> &'a mut W {
563        self.variant(FFE0_BP_MATCH_INTR_EN_A::UNMASK)
564    }
565    #[doc = r"Sets the field bit"]
566    #[inline(always)]
567    pub fn set_bit(self) -> &'a mut W {
568        self.bit(true)
569    }
570    #[doc = r"Clears the field bit"]
571    #[inline(always)]
572    pub fn clear_bit(self) -> &'a mut W {
573        self.bit(false)
574    }
575    #[doc = r"Writes raw bits to the field"]
576    #[inline(always)]
577    pub fn bit(self, value: bool) -> &'a mut W {
578        self.w.bits =
579            (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
580        self.w
581    }
582}
583#[doc = "Set to enable the interrupt, leave cleared to mask"]
584pub type FFE1_OVERRUN_EN_A = SM_MULT_WR_INTR_EN_A;
585#[doc = "Field `FFE1_OVERRUN_EN` reader - Set to enable the interrupt, leave cleared to mask"]
586pub type FFE1_OVERRUN_EN_R = SM_MULT_WR_INTR_EN_R;
587#[doc = "Field `FFE1_OVERRUN_EN` writer - Set to enable the interrupt, leave cleared to mask"]
588pub struct FFE1_OVERRUN_EN_W<'a> {
589    w: &'a mut W,
590}
591impl<'a> FFE1_OVERRUN_EN_W<'a> {
592    #[doc = r"Writes `variant` to the field"]
593    #[inline(always)]
594    pub fn variant(self, variant: FFE1_OVERRUN_EN_A) -> &'a mut W {
595        self.bit(variant.into())
596    }
597    #[doc = "Mask the interrupt event"]
598    #[inline(always)]
599    pub fn mask(self) -> &'a mut W {
600        self.variant(FFE1_OVERRUN_EN_A::MASK)
601    }
602    #[doc = "Unmask the interrupt event"]
603    #[inline(always)]
604    pub fn unmask(self) -> &'a mut W {
605        self.variant(FFE1_OVERRUN_EN_A::UNMASK)
606    }
607    #[doc = r"Sets the field bit"]
608    #[inline(always)]
609    pub fn set_bit(self) -> &'a mut W {
610        self.bit(true)
611    }
612    #[doc = r"Clears the field bit"]
613    #[inline(always)]
614    pub fn clear_bit(self) -> &'a mut W {
615        self.bit(false)
616    }
617    #[doc = r"Writes raw bits to the field"]
618    #[inline(always)]
619    pub fn bit(self, value: bool) -> &'a mut W {
620        self.w.bits =
621            (self.w.bits & !(0x01 << 14)) | ((value as u32 & 0x01) << 14);
622        self.w
623    }
624}
625#[doc = "Set to enable the interrupt, leave cleared to mask"]
626pub type PKFB_OVF_EN_A = SM_MULT_WR_INTR_EN_A;
627#[doc = "Field `PKFB_OVF_EN` reader - Set to enable the interrupt, leave cleared to mask"]
628pub type PKFB_OVF_EN_R = SM_MULT_WR_INTR_EN_R;
629#[doc = "Field `PKFB_OVF_EN` writer - Set to enable the interrupt, leave cleared to mask"]
630pub struct PKFB_OVF_EN_W<'a> {
631    w: &'a mut W,
632}
633impl<'a> PKFB_OVF_EN_W<'a> {
634    #[doc = r"Writes `variant` to the field"]
635    #[inline(always)]
636    pub fn variant(self, variant: PKFB_OVF_EN_A) -> &'a mut W {
637        self.bit(variant.into())
638    }
639    #[doc = "Mask the interrupt event"]
640    #[inline(always)]
641    pub fn mask(self) -> &'a mut W {
642        self.variant(PKFB_OVF_EN_A::MASK)
643    }
644    #[doc = "Unmask the interrupt event"]
645    #[inline(always)]
646    pub fn unmask(self) -> &'a mut W {
647        self.variant(PKFB_OVF_EN_A::UNMASK)
648    }
649    #[doc = r"Sets the field bit"]
650    #[inline(always)]
651    pub fn set_bit(self) -> &'a mut W {
652        self.bit(true)
653    }
654    #[doc = r"Clears the field bit"]
655    #[inline(always)]
656    pub fn clear_bit(self) -> &'a mut W {
657        self.bit(false)
658    }
659    #[doc = r"Writes raw bits to the field"]
660    #[inline(always)]
661    pub fn bit(self, value: bool) -> &'a mut W {
662        self.w.bits =
663            (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
664        self.w
665    }
666}
667#[doc = "Set to enable the interrupt, leave cleared to mask"]
668pub type SM0_BP_MATCH_INTR_EN_A = SM_MULT_WR_INTR_EN_A;
669#[doc = "Field `SM0_BP_MATCH_INTR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
670pub type SM0_BP_MATCH_INTR_EN_R = SM_MULT_WR_INTR_EN_R;
671#[doc = "Field `SM0_BP_MATCH_INTR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
672pub struct SM0_BP_MATCH_INTR_EN_W<'a> {
673    w: &'a mut W,
674}
675impl<'a> SM0_BP_MATCH_INTR_EN_W<'a> {
676    #[doc = r"Writes `variant` to the field"]
677    #[inline(always)]
678    pub fn variant(self, variant: SM0_BP_MATCH_INTR_EN_A) -> &'a mut W {
679        self.bit(variant.into())
680    }
681    #[doc = "Mask the interrupt event"]
682    #[inline(always)]
683    pub fn mask(self) -> &'a mut W {
684        self.variant(SM0_BP_MATCH_INTR_EN_A::MASK)
685    }
686    #[doc = "Unmask the interrupt event"]
687    #[inline(always)]
688    pub fn unmask(self) -> &'a mut W {
689        self.variant(SM0_BP_MATCH_INTR_EN_A::UNMASK)
690    }
691    #[doc = r"Sets the field bit"]
692    #[inline(always)]
693    pub fn set_bit(self) -> &'a mut W {
694        self.bit(true)
695    }
696    #[doc = r"Clears the field bit"]
697    #[inline(always)]
698    pub fn clear_bit(self) -> &'a mut W {
699        self.bit(false)
700    }
701    #[doc = r"Writes raw bits to the field"]
702    #[inline(always)]
703    pub fn bit(self, value: bool) -> &'a mut W {
704        self.w.bits =
705            (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
706        self.w
707    }
708}
709#[doc = "Set to enable the interrupt, leave cleared to mask"]
710pub type SM1_BP_MATCH_INTR_EN_A = SM_MULT_WR_INTR_EN_A;
711#[doc = "Field `SM1_BP_MATCH_INTR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
712pub type SM1_BP_MATCH_INTR_EN_R = SM_MULT_WR_INTR_EN_R;
713#[doc = "Field `SM1_BP_MATCH_INTR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
714pub struct SM1_BP_MATCH_INTR_EN_W<'a> {
715    w: &'a mut W,
716}
717impl<'a> SM1_BP_MATCH_INTR_EN_W<'a> {
718    #[doc = r"Writes `variant` to the field"]
719    #[inline(always)]
720    pub fn variant(self, variant: SM1_BP_MATCH_INTR_EN_A) -> &'a mut W {
721        self.bit(variant.into())
722    }
723    #[doc = "Mask the interrupt event"]
724    #[inline(always)]
725    pub fn mask(self) -> &'a mut W {
726        self.variant(SM1_BP_MATCH_INTR_EN_A::MASK)
727    }
728    #[doc = "Unmask the interrupt event"]
729    #[inline(always)]
730    pub fn unmask(self) -> &'a mut W {
731        self.variant(SM1_BP_MATCH_INTR_EN_A::UNMASK)
732    }
733    #[doc = r"Sets the field bit"]
734    #[inline(always)]
735    pub fn set_bit(self) -> &'a mut W {
736        self.bit(true)
737    }
738    #[doc = r"Clears the field bit"]
739    #[inline(always)]
740    pub fn clear_bit(self) -> &'a mut W {
741        self.bit(false)
742    }
743    #[doc = r"Writes raw bits to the field"]
744    #[inline(always)]
745    pub fn bit(self, value: bool) -> &'a mut W {
746        self.w.bits =
747            (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
748        self.w
749    }
750}
751#[doc = "Set to enable the interrupt, leave cleared to mask"]
752pub type SPI_MS_INTR_EN_A = SM_MULT_WR_INTR_EN_A;
753#[doc = "Field `SPI_MS_INTR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
754pub type SPI_MS_INTR_EN_R = SM_MULT_WR_INTR_EN_R;
755#[doc = "Field `SPI_MS_INTR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
756pub struct SPI_MS_INTR_EN_W<'a> {
757    w: &'a mut W,
758}
759impl<'a> SPI_MS_INTR_EN_W<'a> {
760    #[doc = r"Writes `variant` to the field"]
761    #[inline(always)]
762    pub fn variant(self, variant: SPI_MS_INTR_EN_A) -> &'a mut W {
763        self.bit(variant.into())
764    }
765    #[doc = "Mask the interrupt event"]
766    #[inline(always)]
767    pub fn mask(self) -> &'a mut W {
768        self.variant(SPI_MS_INTR_EN_A::MASK)
769    }
770    #[doc = "Unmask the interrupt event"]
771    #[inline(always)]
772    pub fn unmask(self) -> &'a mut W {
773        self.variant(SPI_MS_INTR_EN_A::UNMASK)
774    }
775    #[doc = r"Sets the field bit"]
776    #[inline(always)]
777    pub fn set_bit(self) -> &'a mut W {
778        self.bit(true)
779    }
780    #[doc = r"Clears the field bit"]
781    #[inline(always)]
782    pub fn clear_bit(self) -> &'a mut W {
783        self.bit(false)
784    }
785    #[doc = r"Writes raw bits to the field"]
786    #[inline(always)]
787    pub fn bit(self, value: bool) -> &'a mut W {
788        self.w.bits =
789            (self.w.bits & !(0x01 << 18)) | ((value as u32 & 0x01) << 18);
790        self.w
791    }
792}
793#[doc = "Set to enable the interrupt, leave cleared to mask"]
794pub type CM_2K_LP_INTR_EN_A = SM_MULT_WR_INTR_EN_A;
795#[doc = "Field `CM_2k_LP_INTR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
796pub type CM_2K_LP_INTR_EN_R = SM_MULT_WR_INTR_EN_R;
797#[doc = "Field `CM_2k_LP_INTR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
798pub struct CM_2K_LP_INTR_EN_W<'a> {
799    w: &'a mut W,
800}
801impl<'a> CM_2K_LP_INTR_EN_W<'a> {
802    #[doc = r"Writes `variant` to the field"]
803    #[inline(always)]
804    pub fn variant(self, variant: CM_2K_LP_INTR_EN_A) -> &'a mut W {
805        self.bit(variant.into())
806    }
807    #[doc = "Mask the interrupt event"]
808    #[inline(always)]
809    pub fn mask(self) -> &'a mut W {
810        self.variant(CM_2K_LP_INTR_EN_A::MASK)
811    }
812    #[doc = "Unmask the interrupt event"]
813    #[inline(always)]
814    pub fn unmask(self) -> &'a mut W {
815        self.variant(CM_2K_LP_INTR_EN_A::UNMASK)
816    }
817    #[doc = r"Sets the field bit"]
818    #[inline(always)]
819    pub fn set_bit(self) -> &'a mut W {
820        self.bit(true)
821    }
822    #[doc = r"Clears the field bit"]
823    #[inline(always)]
824    pub fn clear_bit(self) -> &'a mut W {
825        self.bit(false)
826    }
827    #[doc = r"Writes raw bits to the field"]
828    #[inline(always)]
829    pub fn bit(self, value: bool) -> &'a mut W {
830        self.w.bits =
831            (self.w.bits & !(0x01 << 19)) | ((value as u32 & 0x01) << 19);
832        self.w
833    }
834}
835#[doc = "Set to enable the interrupt, leave cleared to mask"]
836pub type DM2_LP_INTR_EN_A = SM_MULT_WR_INTR_EN_A;
837#[doc = "Field `DM2_LP_INTR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
838pub type DM2_LP_INTR_EN_R = SM_MULT_WR_INTR_EN_R;
839#[doc = "Field `DM2_LP_INTR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
840pub struct DM2_LP_INTR_EN_W<'a> {
841    w: &'a mut W,
842}
843impl<'a> DM2_LP_INTR_EN_W<'a> {
844    #[doc = r"Writes `variant` to the field"]
845    #[inline(always)]
846    pub fn variant(self, variant: DM2_LP_INTR_EN_A) -> &'a mut W {
847        self.bit(variant.into())
848    }
849    #[doc = "Mask the interrupt event"]
850    #[inline(always)]
851    pub fn mask(self) -> &'a mut W {
852        self.variant(DM2_LP_INTR_EN_A::MASK)
853    }
854    #[doc = "Unmask the interrupt event"]
855    #[inline(always)]
856    pub fn unmask(self) -> &'a mut W {
857        self.variant(DM2_LP_INTR_EN_A::UNMASK)
858    }
859    #[doc = r"Sets the field bit"]
860    #[inline(always)]
861    pub fn set_bit(self) -> &'a mut W {
862        self.bit(true)
863    }
864    #[doc = r"Clears the field bit"]
865    #[inline(always)]
866    pub fn clear_bit(self) -> &'a mut W {
867        self.bit(false)
868    }
869    #[doc = r"Writes raw bits to the field"]
870    #[inline(always)]
871    pub fn bit(self, value: bool) -> &'a mut W {
872        self.w.bits =
873            (self.w.bits & !(0x01 << 20)) | ((value as u32 & 0x01) << 20);
874        self.w
875    }
876}
877#[doc = "Set to enable the interrupt, leave cleared to mask"]
878pub type DM3_LP_INTR_EN_A = SM_MULT_WR_INTR_EN_A;
879#[doc = "Field `DM3_LP_INTR_EN` reader - Set to enable the interrupt, leave cleared to mask"]
880pub type DM3_LP_INTR_EN_R = SM_MULT_WR_INTR_EN_R;
881#[doc = "Field `DM3_LP_INTR_EN` writer - Set to enable the interrupt, leave cleared to mask"]
882pub struct DM3_LP_INTR_EN_W<'a> {
883    w: &'a mut W,
884}
885impl<'a> DM3_LP_INTR_EN_W<'a> {
886    #[doc = r"Writes `variant` to the field"]
887    #[inline(always)]
888    pub fn variant(self, variant: DM3_LP_INTR_EN_A) -> &'a mut W {
889        self.bit(variant.into())
890    }
891    #[doc = "Mask the interrupt event"]
892    #[inline(always)]
893    pub fn mask(self) -> &'a mut W {
894        self.variant(DM3_LP_INTR_EN_A::MASK)
895    }
896    #[doc = "Unmask the interrupt event"]
897    #[inline(always)]
898    pub fn unmask(self) -> &'a mut W {
899        self.variant(DM3_LP_INTR_EN_A::UNMASK)
900    }
901    #[doc = r"Sets the field bit"]
902    #[inline(always)]
903    pub fn set_bit(self) -> &'a mut W {
904        self.bit(true)
905    }
906    #[doc = r"Clears the field bit"]
907    #[inline(always)]
908    pub fn clear_bit(self) -> &'a mut W {
909        self.bit(false)
910    }
911    #[doc = r"Writes raw bits to the field"]
912    #[inline(always)]
913    pub fn bit(self, value: bool) -> &'a mut W {
914        self.w.bits =
915            (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21);
916        self.w
917    }
918}
919#[doc = "Set to enable the interrupt, leave cleared to mask"]
920pub type AHBM_BUS_ERROR_INTR_EN_A = SM_MULT_WR_INTR_EN_A;
921#[doc = "Field `ahbm_bus_error_intr_en` reader - Set to enable the interrupt, leave cleared to mask"]
922pub type AHBM_BUS_ERROR_INTR_EN_R = SM_MULT_WR_INTR_EN_R;
923#[doc = "Field `ahbm_bus_error_intr_en` writer - Set to enable the interrupt, leave cleared to mask"]
924pub struct AHBM_BUS_ERROR_INTR_EN_W<'a> {
925    w: &'a mut W,
926}
927impl<'a> AHBM_BUS_ERROR_INTR_EN_W<'a> {
928    #[doc = r"Writes `variant` to the field"]
929    #[inline(always)]
930    pub fn variant(self, variant: AHBM_BUS_ERROR_INTR_EN_A) -> &'a mut W {
931        self.bit(variant.into())
932    }
933    #[doc = "Mask the interrupt event"]
934    #[inline(always)]
935    pub fn mask(self) -> &'a mut W {
936        self.variant(AHBM_BUS_ERROR_INTR_EN_A::MASK)
937    }
938    #[doc = "Unmask the interrupt event"]
939    #[inline(always)]
940    pub fn unmask(self) -> &'a mut W {
941        self.variant(AHBM_BUS_ERROR_INTR_EN_A::UNMASK)
942    }
943    #[doc = r"Sets the field bit"]
944    #[inline(always)]
945    pub fn set_bit(self) -> &'a mut W {
946        self.bit(true)
947    }
948    #[doc = r"Clears the field bit"]
949    #[inline(always)]
950    pub fn clear_bit(self) -> &'a mut W {
951        self.bit(false)
952    }
953    #[doc = r"Writes raw bits to the field"]
954    #[inline(always)]
955    pub fn bit(self, value: bool) -> &'a mut W {
956        self.w.bits =
957            (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
958        self.w
959    }
960}
961impl R {
962    #[doc = "Bit 0 - Set to enable the interrupt, leave cleared to mask"]
963    #[inline(always)]
964    pub fn sm_mult_wr_intr_en(&self) -> SM_MULT_WR_INTR_EN_R {
965        SM_MULT_WR_INTR_EN_R::new((self.bits & 0x01) != 0)
966    }
967    #[doc = "Bit 1 - Set to enable the interrupt, leave cleared to mask"]
968    #[inline(always)]
969    pub fn ffe0_overrun_en(&self) -> FFE0_OVERRUN_EN_R {
970        FFE0_OVERRUN_EN_R::new(((self.bits >> 1) & 0x01) != 0)
971    }
972    #[doc = "Bit 4 - Set to enable the interrupt, leave cleared to mask"]
973    #[inline(always)]
974    pub fn ffe0_sm1_overrun_en(&self) -> FFE0_SM1_OVERRUN_EN_R {
975        FFE0_SM1_OVERRUN_EN_R::new(((self.bits >> 4) & 0x01) != 0)
976    }
977    #[doc = "Bit 5 - Set to enable the interrupt, leave cleared to mask"]
978    #[inline(always)]
979    pub fn ffe0_sm0_overrun_en(&self) -> FFE0_SM0_OVERRUN_EN_R {
980        FFE0_SM0_OVERRUN_EN_R::new(((self.bits >> 5) & 0x01) != 0)
981    }
982    #[doc = "Bit 6 - Set to enable the interrupt, leave cleared to mask"]
983    #[inline(always)]
984    pub fn i2c_ms_1_error_en(&self) -> I2C_MS_1_ERROR_EN_R {
985        I2C_MS_1_ERROR_EN_R::new(((self.bits >> 6) & 0x01) != 0)
986    }
987    #[doc = "Bit 7 - Set to enable the interrupt, leave cleared to mask"]
988    #[inline(always)]
989    pub fn i2c_ms_0_error_en(&self) -> I2C_MS_0_ERROR_EN_R {
990        I2C_MS_0_ERROR_EN_R::new(((self.bits >> 7) & 0x01) != 0)
991    }
992    #[doc = "Bit 8 - Set to enable the interrupt, leave cleared to mask"]
993    #[inline(always)]
994    pub fn cm_8k_lp_intr_en(&self) -> CM_8K_LP_INTR_EN_R {
995        CM_8K_LP_INTR_EN_R::new(((self.bits >> 8) & 0x01) != 0)
996    }
997    #[doc = "Bit 9 - Set to enable the interrupt, leave cleared to mask"]
998    #[inline(always)]
999    pub fn dm0_lp_intr_en(&self) -> DM0_LP_INTR_EN_R {
1000        DM0_LP_INTR_EN_R::new(((self.bits >> 9) & 0x01) != 0)
1001    }
1002    #[doc = "Bit 10 - Set to enable the interrupt, leave cleared to mask"]
1003    #[inline(always)]
1004    pub fn dm1_lp_intr_en(&self) -> DM1_LP_INTR_EN_R {
1005        DM1_LP_INTR_EN_R::new(((self.bits >> 10) & 0x01) != 0)
1006    }
1007    #[doc = "Bit 11 - Set to enable the interrupt, leave cleared to mask"]
1008    #[inline(always)]
1009    pub fn sm0_lp_intr_en(&self) -> SM0_LP_INTR_EN_R {
1010        SM0_LP_INTR_EN_R::new(((self.bits >> 11) & 0x01) != 0)
1011    }
1012    #[doc = "Bit 12 - Set to enable the interrupt, leave cleared to mask"]
1013    #[inline(always)]
1014    pub fn sm1_lp_intr_en(&self) -> SM1_LP_INTR_EN_R {
1015        SM1_LP_INTR_EN_R::new(((self.bits >> 12) & 0x01) != 0)
1016    }
1017    #[doc = "Bit 13 - Set to enable the interrupt, leave cleared to mask"]
1018    #[inline(always)]
1019    pub fn ffe0_bp_match_intr_en(&self) -> FFE0_BP_MATCH_INTR_EN_R {
1020        FFE0_BP_MATCH_INTR_EN_R::new(((self.bits >> 13) & 0x01) != 0)
1021    }
1022    #[doc = "Bit 14 - Set to enable the interrupt, leave cleared to mask"]
1023    #[inline(always)]
1024    pub fn ffe1_overrun_en(&self) -> FFE1_OVERRUN_EN_R {
1025        FFE1_OVERRUN_EN_R::new(((self.bits >> 14) & 0x01) != 0)
1026    }
1027    #[doc = "Bit 15 - Set to enable the interrupt, leave cleared to mask"]
1028    #[inline(always)]
1029    pub fn pkfb_ovf_en(&self) -> PKFB_OVF_EN_R {
1030        PKFB_OVF_EN_R::new(((self.bits >> 15) & 0x01) != 0)
1031    }
1032    #[doc = "Bit 16 - Set to enable the interrupt, leave cleared to mask"]
1033    #[inline(always)]
1034    pub fn sm0_bp_match_intr_en(&self) -> SM0_BP_MATCH_INTR_EN_R {
1035        SM0_BP_MATCH_INTR_EN_R::new(((self.bits >> 16) & 0x01) != 0)
1036    }
1037    #[doc = "Bit 17 - Set to enable the interrupt, leave cleared to mask"]
1038    #[inline(always)]
1039    pub fn sm1_bp_match_intr_en(&self) -> SM1_BP_MATCH_INTR_EN_R {
1040        SM1_BP_MATCH_INTR_EN_R::new(((self.bits >> 17) & 0x01) != 0)
1041    }
1042    #[doc = "Bit 18 - Set to enable the interrupt, leave cleared to mask"]
1043    #[inline(always)]
1044    pub fn spi_ms_intr_en(&self) -> SPI_MS_INTR_EN_R {
1045        SPI_MS_INTR_EN_R::new(((self.bits >> 18) & 0x01) != 0)
1046    }
1047    #[doc = "Bit 19 - Set to enable the interrupt, leave cleared to mask"]
1048    #[inline(always)]
1049    pub fn cm_2k_lp_intr_en(&self) -> CM_2K_LP_INTR_EN_R {
1050        CM_2K_LP_INTR_EN_R::new(((self.bits >> 19) & 0x01) != 0)
1051    }
1052    #[doc = "Bit 20 - Set to enable the interrupt, leave cleared to mask"]
1053    #[inline(always)]
1054    pub fn dm2_lp_intr_en(&self) -> DM2_LP_INTR_EN_R {
1055        DM2_LP_INTR_EN_R::new(((self.bits >> 20) & 0x01) != 0)
1056    }
1057    #[doc = "Bit 21 - Set to enable the interrupt, leave cleared to mask"]
1058    #[inline(always)]
1059    pub fn dm3_lp_intr_en(&self) -> DM3_LP_INTR_EN_R {
1060        DM3_LP_INTR_EN_R::new(((self.bits >> 21) & 0x01) != 0)
1061    }
1062    #[doc = "Bit 22 - Set to enable the interrupt, leave cleared to mask"]
1063    #[inline(always)]
1064    pub fn ahbm_bus_error_intr_en(&self) -> AHBM_BUS_ERROR_INTR_EN_R {
1065        AHBM_BUS_ERROR_INTR_EN_R::new(((self.bits >> 22) & 0x01) != 0)
1066    }
1067}
1068impl W {
1069    #[doc = "Bit 0 - Set to enable the interrupt, leave cleared to mask"]
1070    #[inline(always)]
1071    pub fn sm_mult_wr_intr_en(&mut self) -> SM_MULT_WR_INTR_EN_W {
1072        SM_MULT_WR_INTR_EN_W { w: self }
1073    }
1074    #[doc = "Bit 1 - Set to enable the interrupt, leave cleared to mask"]
1075    #[inline(always)]
1076    pub fn ffe0_overrun_en(&mut self) -> FFE0_OVERRUN_EN_W {
1077        FFE0_OVERRUN_EN_W { w: self }
1078    }
1079    #[doc = "Bit 4 - Set to enable the interrupt, leave cleared to mask"]
1080    #[inline(always)]
1081    pub fn ffe0_sm1_overrun_en(&mut self) -> FFE0_SM1_OVERRUN_EN_W {
1082        FFE0_SM1_OVERRUN_EN_W { w: self }
1083    }
1084    #[doc = "Bit 5 - Set to enable the interrupt, leave cleared to mask"]
1085    #[inline(always)]
1086    pub fn ffe0_sm0_overrun_en(&mut self) -> FFE0_SM0_OVERRUN_EN_W {
1087        FFE0_SM0_OVERRUN_EN_W { w: self }
1088    }
1089    #[doc = "Bit 6 - Set to enable the interrupt, leave cleared to mask"]
1090    #[inline(always)]
1091    pub fn i2c_ms_1_error_en(&mut self) -> I2C_MS_1_ERROR_EN_W {
1092        I2C_MS_1_ERROR_EN_W { w: self }
1093    }
1094    #[doc = "Bit 7 - Set to enable the interrupt, leave cleared to mask"]
1095    #[inline(always)]
1096    pub fn i2c_ms_0_error_en(&mut self) -> I2C_MS_0_ERROR_EN_W {
1097        I2C_MS_0_ERROR_EN_W { w: self }
1098    }
1099    #[doc = "Bit 8 - Set to enable the interrupt, leave cleared to mask"]
1100    #[inline(always)]
1101    pub fn cm_8k_lp_intr_en(&mut self) -> CM_8K_LP_INTR_EN_W {
1102        CM_8K_LP_INTR_EN_W { w: self }
1103    }
1104    #[doc = "Bit 9 - Set to enable the interrupt, leave cleared to mask"]
1105    #[inline(always)]
1106    pub fn dm0_lp_intr_en(&mut self) -> DM0_LP_INTR_EN_W {
1107        DM0_LP_INTR_EN_W { w: self }
1108    }
1109    #[doc = "Bit 10 - Set to enable the interrupt, leave cleared to mask"]
1110    #[inline(always)]
1111    pub fn dm1_lp_intr_en(&mut self) -> DM1_LP_INTR_EN_W {
1112        DM1_LP_INTR_EN_W { w: self }
1113    }
1114    #[doc = "Bit 11 - Set to enable the interrupt, leave cleared to mask"]
1115    #[inline(always)]
1116    pub fn sm0_lp_intr_en(&mut self) -> SM0_LP_INTR_EN_W {
1117        SM0_LP_INTR_EN_W { w: self }
1118    }
1119    #[doc = "Bit 12 - Set to enable the interrupt, leave cleared to mask"]
1120    #[inline(always)]
1121    pub fn sm1_lp_intr_en(&mut self) -> SM1_LP_INTR_EN_W {
1122        SM1_LP_INTR_EN_W { w: self }
1123    }
1124    #[doc = "Bit 13 - Set to enable the interrupt, leave cleared to mask"]
1125    #[inline(always)]
1126    pub fn ffe0_bp_match_intr_en(&mut self) -> FFE0_BP_MATCH_INTR_EN_W {
1127        FFE0_BP_MATCH_INTR_EN_W { w: self }
1128    }
1129    #[doc = "Bit 14 - Set to enable the interrupt, leave cleared to mask"]
1130    #[inline(always)]
1131    pub fn ffe1_overrun_en(&mut self) -> FFE1_OVERRUN_EN_W {
1132        FFE1_OVERRUN_EN_W { w: self }
1133    }
1134    #[doc = "Bit 15 - Set to enable the interrupt, leave cleared to mask"]
1135    #[inline(always)]
1136    pub fn pkfb_ovf_en(&mut self) -> PKFB_OVF_EN_W {
1137        PKFB_OVF_EN_W { w: self }
1138    }
1139    #[doc = "Bit 16 - Set to enable the interrupt, leave cleared to mask"]
1140    #[inline(always)]
1141    pub fn sm0_bp_match_intr_en(&mut self) -> SM0_BP_MATCH_INTR_EN_W {
1142        SM0_BP_MATCH_INTR_EN_W { w: self }
1143    }
1144    #[doc = "Bit 17 - Set to enable the interrupt, leave cleared to mask"]
1145    #[inline(always)]
1146    pub fn sm1_bp_match_intr_en(&mut self) -> SM1_BP_MATCH_INTR_EN_W {
1147        SM1_BP_MATCH_INTR_EN_W { w: self }
1148    }
1149    #[doc = "Bit 18 - Set to enable the interrupt, leave cleared to mask"]
1150    #[inline(always)]
1151    pub fn spi_ms_intr_en(&mut self) -> SPI_MS_INTR_EN_W {
1152        SPI_MS_INTR_EN_W { w: self }
1153    }
1154    #[doc = "Bit 19 - Set to enable the interrupt, leave cleared to mask"]
1155    #[inline(always)]
1156    pub fn cm_2k_lp_intr_en(&mut self) -> CM_2K_LP_INTR_EN_W {
1157        CM_2K_LP_INTR_EN_W { w: self }
1158    }
1159    #[doc = "Bit 20 - Set to enable the interrupt, leave cleared to mask"]
1160    #[inline(always)]
1161    pub fn dm2_lp_intr_en(&mut self) -> DM2_LP_INTR_EN_W {
1162        DM2_LP_INTR_EN_W { w: self }
1163    }
1164    #[doc = "Bit 21 - Set to enable the interrupt, leave cleared to mask"]
1165    #[inline(always)]
1166    pub fn dm3_lp_intr_en(&mut self) -> DM3_LP_INTR_EN_W {
1167        DM3_LP_INTR_EN_W { w: self }
1168    }
1169    #[doc = "Bit 22 - Set to enable the interrupt, leave cleared to mask"]
1170    #[inline(always)]
1171    pub fn ahbm_bus_error_intr_en(&mut self) -> AHBM_BUS_ERROR_INTR_EN_W {
1172        AHBM_BUS_ERROR_INTR_EN_W { w: self }
1173    }
1174    #[doc = "Writes raw bits to the register."]
1175    #[inline(always)]
1176    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
1177        self.0.bits(bits);
1178        self
1179    }
1180}
1181#[doc = "Control the masking for different Flexible Fusion Engine interrupts\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [interrupt_en](index.html) module"]
1182pub struct INTERRUPT_EN_SPEC;
1183impl crate::RegisterSpec for INTERRUPT_EN_SPEC {
1184    type Ux = u32;
1185}
1186#[doc = "`read()` method returns [interrupt_en::R](R) reader structure"]
1187impl crate::Readable for INTERRUPT_EN_SPEC {
1188    type Reader = R;
1189}
1190#[doc = "`write(|w| ..)` method takes [interrupt_en::W](W) writer structure"]
1191impl crate::Writable for INTERRUPT_EN_SPEC {
1192    type Writer = W;
1193}
1194#[doc = "`reset()` method sets INTERRUPT_EN to value 0"]
1195impl crate::Resettable for INTERRUPT_EN_SPEC {
1196    #[inline(always)]
1197    fn reset_value() -> Self::Ux {
1198        0
1199    }
1200}
eos_s3/ext_regs_ffe/interrupt_en.rs

eos_s3/ext_regs_ffe/
interrupt_en.rs
